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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by PAXPR04MB9641.eurprd04.prod.outlook.com (2603:10a6:102:23f::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8048.16; Thu, 10 Oct 2024 07:14:54 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::d1ce:ea15:6648:6f90%4]) with mapi id 15.20.8048.017; Thu, 10 Oct 2024 07:14:54 +0000 Message-ID: Date: Thu, 10 Oct 2024 15:15:19 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] drm: bridge: ldb: Configure LDB clock in .mode_set To: Marek Vasut , dri-devel@lists.freedesktop.org Cc: Abel Vesa , Andrzej Hajda , David Airlie , Fabio Estevam , Isaac Scott , Jernej Skrabec , Jonas Karlman , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Michael Turquette , Neil Armstrong , Peng Fan , Pengutronix Kernel Team , Robert Foss , Sascha Hauer , Shawn Guo , Simona Vetter , Stephen Boyd , Thomas Zimmermann , imx@lists.linux.dev, kernel@dh-electronics.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org References: <20241008223846.337162-1-marex@denx.de> <20241008223846.337162-2-marex@denx.de> From: Liu Ying Content-Language: en-US In-Reply-To: <20241008223846.337162-2-marex@denx.de> Content-Type: text/plain; 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Make sure the serializer clock and their > upstream Video PLL are configured early in .mode_set to the x7 or x14 > rate of pixel clock, before LCDIFv3 .atomic_enable is called which would > configure the Video PLL to low x1 rate, which is unusable. > > With this patch in place, the clock tree is correctly configured. The > example below is for a 71.1 MHz pixel clock panel, the LDB serializer > clock is then 497.7 MHz: > > video_pll1_ref_sel 1 1 0 24000000 0 0 50000 > video_pll1 1 1 0 497700000 0 0 50000 > video_pll1_bypass 1 1 0 497700000 0 0 50000 > video_pll1_out 2 2 0 497700000 0 0 50000 > media_ldb 1 1 0 497700000 0 0 50000 > media_ldb_root_clk 1 1 0 497700000 0 0 50000 > media_disp2_pix 1 1 0 71100000 0 0 50000 > media_disp2_pix_root_clk 1 1 0 71100000 0 0 50000 > > Signed-off-by: Marek Vasut > --- > Cc: Abel Vesa > Cc: Andrzej Hajda > Cc: David Airlie > Cc: Fabio Estevam > Cc: Isaac Scott > Cc: Jernej Skrabec > Cc: Jonas Karlman > Cc: Laurent Pinchart > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Michael Turquette > Cc: Neil Armstrong > Cc: Peng Fan > Cc: Pengutronix Kernel Team > Cc: Robert Foss > Cc: Sascha Hauer > Cc: Shawn Guo > Cc: Simona Vetter > Cc: Stephen Boyd > Cc: Thomas Zimmermann > Cc: dri-devel@lists.freedesktop.org > Cc: imx@lists.linux.dev > Cc: kernel@dh-electronics.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-clk@vger.kernel.org > --- > drivers/gpu/drm/bridge/fsl-ldb.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c > index 0e4bac7dd04ff..a3a31467fcc85 100644 > --- a/drivers/gpu/drm/bridge/fsl-ldb.c > +++ b/drivers/gpu/drm/bridge/fsl-ldb.c > @@ -278,6 +278,16 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, > return MODE_OK; > } > > +static void fsl_ldb_mode_set(struct drm_bridge *bridge, > + const struct drm_display_mode *mode, > + const struct drm_display_mode *adj) > +{ > + struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); > + unsigned long requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); > + > + clk_set_rate(fsl_ldb->clk, requested_link_freq); The mode_set callback won't be called when only crtc_state->active is changed from false to true in an atomic commit, e.g., blanking the emulated fbdev first and then unblanking it. So, in this case, the clk_set_rate() in fsl_ldb_atomic_enable() is still called after those from mxsfb_kms or lcdif_kms. Also, it doesn't look neat to call clk_set_rate() from both mode_set callback and atomic_enable callback. The idea is to assign a reasonable PLL clock rate in DT to make display drivers' life easier, especially for i.MX8MP where LDB, Samsung MIPI DSI may use a single PLL at the same time. > +} > + > static const struct drm_bridge_funcs funcs = { > .attach = fsl_ldb_attach, > .atomic_enable = fsl_ldb_atomic_enable, > @@ -287,6 +297,7 @@ static const struct drm_bridge_funcs funcs = { > .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts, > .atomic_reset = drm_atomic_helper_bridge_reset, > .mode_valid = fsl_ldb_mode_valid, > + .mode_set = fsl_ldb_mode_set, > }; > > static int fsl_ldb_probe(struct platform_device *pdev) -- Regards, Liu Ying