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Message-ID: <d9c185a3-6176-7b37-c87a-498877f69c4a@starfivetech.com>
Date:   Mon, 20 Mar 2023 10:41:04 +0800
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Subject: Re: [PATCH v2 1/6] dt-bindings: clock: Add StarFive JH7110 PLL clock
 generator
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CC:     <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
        "Stephen Boyd" <sboyd@kernel.org>,
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        Emil Renner Berthing <kernel@esmil.dk>,
        Michael Turquette <mturquette@baylibre.com>,
        Rob Herring <robh+dt@kernel.org>,
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        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        William Qiu <william.qiu@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
References: <20230316030514.137427-1-xingyu.wu@starfivetech.com>
 <20230316030514.137427-2-xingyu.wu@starfivetech.com>
 <95b1f70d-b7ba-370f-12c4-bf7a518ffe3e@linaro.org>
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From:   Xingyu Wu <xingyu.wu@starfivetech.com>
In-Reply-To: <95b1f70d-b7ba-370f-12c4-bf7a518ffe3e@linaro.org>
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On 2023/3/19 20:25, Krzysztof Kozlowski wrote:
> On 16/03/2023 04:05, Xingyu Wu wrote:
>> Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
>> 
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> 
> 
>> +
>> +examples:
>> +  - |
>> +    pllclk: pll-clock-controller {
> 
> This should be just "clock-controller" (and drop the label).

Will modify to "clock-controller" and drop the label.
Thanks.

> 
> With above
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 

Best regards,
Xingyu Wu