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Tue, 20 May 2025 15:58:15 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B91E140048; Tue, 20 May 2025 15:56:55 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3FFC3B1082D; Tue, 20 May 2025 15:55:25 +0200 (CEST) Received: from [10.48.87.146] (10.48.87.146) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 20 May 2025 15:55:24 +0200 Message-ID: Date: Tue, 20 May 2025 15:55:23 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: stm32: add STM32MP21 clocks and reset bindings To: ALOK TIWARI , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel CC: , , , , , Nicolas Le Bayon References: <20250519142057.260549-1-gabriel.fernandez@foss.st.com> <20250519142057.260549-2-gabriel.fernandez@foss.st.com> <83ce3ca8-c014-4814-8c51-9f7fd5151a41@oracle.com> Content-Language: en-US From: Gabriel FERNANDEZ In-Reply-To: <83ce3ca8-c014-4814-8c51-9f7fd5151a41@oracle.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-20_06,2025-05-16_03,2025-03-28_01 On 5/19/25 16:42, ALOK TIWARI wrote: > >> +++ b/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml >> @@ -0,0 +1,200 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: >> https://urldefense.com/v3/__http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml*__;Iw!!ACWV5N9M2RV99hQ!Nqfcj0yvl-cb4Mu6XFbLz7FVSHkQfpdQGRbVtM1EqANq9n_cdZZNBg-YGSqb-Nkm16LDOQ7TsRAIi2iDug6DIO8uPU0kq3E$ >> +$schema: >> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!ACWV5N9M2RV99hQ!Nqfcj0yvl-cb4Mu6XFbLz7FVSHkQfpdQGRbVtM1EqANq9n_cdZZNBg-YGSqb-Nkm16LDOQ7TsRAIi2iDug6DIO8uLNFOSgg$ >> + >> +title: STM32MP21 Reset Clock Controller >> + >> +maintainers: >> +  - Gabriel Fernandez >> + >> +description: | >> +  The RCC hardware block is both a reset and a clock controller. >> +  RCC makes also power management (resume/supend). > > typo supend > Hi Alok, Thanks for you review done >> + >> +  See also:: >> +    include/dt-bindings/clock/st,stm32mp21-rcc.h >> +    include/dt-bindings/reset/st,stm32mp21-rcc.h >> + > [clip] >> +      - description: CK_SCMI_ICN_APB2 Peripheral bridge 2 >> +      - description: CK_SCMI_ICN_APB3 Peripheral bridge 3 >> +      - description: CK_SCMI_ICN_APB4 Peripheral bridge 4 >> +      - description: CK_SCMI_ICN_APB5 Peripheral bridge 5 >> +      - description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub > > typo degub done Best regards, Gabriel > >> +      - description: CK_SCMI_TIMG1 Peripheral bridge for timer1 >> +      - description: CK_SCMI_TIMG2 Peripheral bridge for timer2 > > Thanks, > Alok