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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Pengyu Luo <mitltlatltl@gmail.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src
Date: Mon, 23 Mar 2026 13:54:29 +0100	[thread overview]
Message-ID: <dda88cb7-090b-4baf-91f7-e6724b506134@oss.qualcomm.com> (raw)
In-Reply-To: <20260321095029.2259489-1-mitltlatltl@gmail.com>

On 3/21/26 10:50 AM, Pengyu Luo wrote:
> Recently, when testing 10-bit dsi C-PHY panel, clks are different
> from the usual. (dsi0_phy_pll_out_dsiclk's parent is dsi0_pll_bit_clk
> now (dsiclk_sel = 0)) And we failed to set dsiclk's children.
> 
> dsi_link_clk_set_rate_6g: Set clk rates: pclk=172992000, byteclk=108120000
> 
> byteclk was set first to 108120000, so the vco rate was set to
> 108120000 * 7 * 1 * 1 = 756840000. When we was trying to set
> 172992000 on mdss_pixel_clk_src later.
> 
> Since there was no matched ratio, we failed to set it. And dsiclk
> divider ratio was set to 15:1 (wrong cached register value 0xf and
> didn't update), we finally got 50455997, apparently wrong.
> 
>   dsi0vco_clk                1       1        0        756839941
>      dsi0_pll_out_div_clk    1       1        0        756839941
>         dsi0_pll_post_out_div_clk 0       0        0        216239983
>         dsi0_pll_bit_clk     2       2        0        756839941
>            dsi0_phy_pll_out_dsiclk 2       2        0        50455997
>               disp_cc_mdss_pclk1_clk_src 1       1        0        50455997
>            dsi0_pll_by_2_bit_clk 0       0        0        378419970
>            dsi0_phy_pll_out_byteclk 2       2        0        108119991
>               disp_cc_mdss_byte1_clk_src 2       2        0        108119991
> 
> Downstream clk_summary shows the mdss_pixel_clk_src support the
> ratio(35:16)
> 
>  dsi0_phy_pll_out_dsiclk             2       2        0        378420000
>      disp_cc_mdss_pclk1_clk_src       1       1        0        172992000
>  dsi0_phy_pll_out_byteclk            2       2        0        108120000
>      disp_cc_mdss_byte1_clk_src       2       2        0        108120000
> 
> After checking downstream source, 15:4 also seems to be supported,
> add them two.

I don't see that, not even in the newest releases.. Is there even a reason
we have to list these divider pairs in the first place?

Konrad

  parent reply	other threads:[~2026-03-23 12:54 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-21  9:50 [PATCH] clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src Pengyu Luo
2026-03-21 21:46 ` Dmitry Baryshkov
2026-03-23  4:24 ` Taniya Das
2026-03-23  4:26 ` Taniya Das
2026-03-23 12:54 ` Konrad Dybcio [this message]
2026-03-23 19:23   ` Dmitry Baryshkov
2026-03-24  9:22     ` Konrad Dybcio
2026-03-24 12:56       ` Pengyu Luo
2026-03-24 13:00         ` Konrad Dybcio
2026-03-24  3:05 ` Bjorn Andersson

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