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Tue, 28 Apr 2026 10:22:27 -0700 (PDT) X-Received: by 2002:a05:6a00:2e82:b0:829:8a84:b9fc with SMTP id d2e1a72fcca58-834dda630bcmr4374538b3a.8.1777396946487; Tue, 28 Apr 2026 10:22:26 -0700 (PDT) Received: from [192.168.1.4] ([122.177.243.58]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834dae0091asm3473988b3a.10.2026.04.28.10.22.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Apr 2026 10:22:26 -0700 (PDT) Message-ID: Date: Tue, 28 Apr 2026 22:52:17 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jagadeesh Kona Subject: Re: [PATCH 07/13] clk: qcom: clk-alpha-pll: Add support to skip PLL configuration To: Konrad Dybcio , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Neil Armstrong , Lee Jones , Ajit Pandey , Imran Shaik , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Maulik Shah , Taniya Das References: <20260420-cesta-sm870-dispcc-v1-0-eb27d845df9c@oss.qualcomm.com> <20260420-cesta-sm870-dispcc-v1-7-eb27d845df9c@oss.qualcomm.com> <5vkpjjuq6vh2mr4lcq5cwqd4h5cbserf3n756d465kheuwl5fk@tu3amjwe5k57> <269bdec3-6340-4b27-9b38-3fc1dfc958c8@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <269bdec3-6340-4b27-9b38-3fc1dfc958c8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=abJRWxot c=1 sm=1 tr=0 ts=69f0ecd3 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=EwI1ikYXukqkrg4G3Narhw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=uU37CDhMaAXootqMB7UA:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: ZqUFBMNBuUP52ywCjBzfb60ykYZKVkst X-Proofpoint-ORIG-GUID: ZqUFBMNBuUP52ywCjBzfb60ykYZKVkst X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI4MDE2NyBTYWx0ZWRfXyn1iv9b3cnKT Lyj+xlkU7W9H4725s9KAPDZRiEtW7SRNyy894/1U3T+w6w271BL8dFOh78zAq5zdMEg7W6f5AoM 5PcGnQRAIoa+HLPHte1yPVRu94pMvO+Kz0SyG+F6xqtXvgw6w88eR07qojsJ7HZYvcizC73vCbd Sy/5hDOeFypOGcfxqnqkYmPhWmq77oI9TzGCSyKFEBY9V0cP9+f/D0O0gEH8rl7bv1jrdu8bNmd LQ77DwO7VfEdhSqhdP+BjSx0UVCm6r6n6FOW4xB+OkoaOzqML5DOZNJ+KIHaLSnQt5Byd1jHZlo KncCdLaNuj6PMx3uHm4HBnEfXtaXMV/tfdg9XFhtUNrNvxH7MmSs74A22BES1jANSFKynhBwZYP EopzPLBP3D9QuizIu/mZ6bGrdFd4lDPOWu0P62GwnzCGWqIEyQiK5gjbJJxsP/c8sTDracJjHNp LlHWb2o/qSSydVe2ZWQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280167 On 4/23/2026 4:43 PM, Konrad Dybcio wrote: > On 4/22/26 8:28 PM, Dmitry Baryshkov wrote: >> On Mon, Apr 20, 2026 at 09:59:00PM +0530, Jagadeesh Kona wrote: >>> Some PLLs are already configured as part of CRM(CESTA Resource >>> manager) initialization. Add support to skip PLL reconfiguration >>> for such PLLs that are already configured. >>> >>> Signed-off-by: Jagadeesh Kona >>> --- >>> drivers/clk/qcom/clk-alpha-pll.c | 8 +++++++- >>> 1 file changed, 7 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c >>> index 67fc97739d0d4c26aec0bac5d43d1b87d297bc6a..2f4ebf4d3884b92c981dbe0e67245704a88881ad 100644 >>> --- a/drivers/clk/qcom/clk-alpha-pll.c >>> +++ b/drivers/clk/qcom/clk-alpha-pll.c >>> @@ -2332,7 +2332,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); >>> void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >>> const struct alpha_pll_config *config) >>> { >>> - u32 lval = config->l; >>> + u32 lval = config->l, regval; >>> >>> /* >>> * If the bootloader left the PLL enabled it's likely that there are >>> @@ -2343,6 +2343,12 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma >>> return; >>> } >>> >>> + /* Return early if PLL is already configured */ >>> + regmap_read(regmap, PLL_L_VAL(pll), ®val); >>> + regval &= LUCID_EVO_PLL_L_VAL_MASK; >>> + if (regval) >>> + return; >>> + >> >> Why is it being applied only to Lucid EVO PLLs? > Thanks Dmitry and Konrad for your reviews. This is the function used to configure all Taycan PLLs, currently all the PLLs configured during CESTA initialization belong to Taycan type only. I will recheck if similar logic is required for any additional PLL types also. > These clocks already have a an .is_enabled() callback, could that be > treated as equivalent? > We already have is_enabled check to avoid configuring PLL's that are already enabled. There can be case where PLL is configured from bootloader but not enabled during bootup. This check avoids re-configuring such PLLs that are already configured by bootloader but not enabled. Thanks, Jagadeesh