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([2a01:e0a:982:cbb0:8ce3:ff4e:ae9b:55f3]) by smtp.gmail.com with ESMTPSA id f12-20020a05600c154c00b003b4931eb435sm2044258wmg.26.2022.09.21.00.19.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Sep 2022 00:19:19 -0700 (PDT) Message-ID: Date: Wed, 21 Sep 2022 09:19:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v2 2/2] clk: qcom: rpmhcc: add sdm670 clocks Content-Language: en-US To: Richard Acayan , linux-arm-msm@vger.kernel.org Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Taniya Das , linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20220920223734.151135-1-mailingradian@gmail.com> <20220920223734.151135-3-mailingradian@gmail.com> From: Neil Armstrong Organization: Linaro In-Reply-To: <20220920223734.151135-3-mailingradian@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 21/09/2022 00:37, Richard Acayan wrote: > The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in > SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail > to resolve a clock. > > Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7 > Signed-off-by: Richard Acayan > --- > drivers/clk/qcom/clk-rpmh.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index c07cab6905cb..82d87a0602fe 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -382,6 +382,26 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = { > .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), > }; > > +static struct clk_hw *sdm670_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw, > + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw, > + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw, > + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw, > + [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw, > + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw, > + [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw, > + [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw, > + [RPMH_IPA_CLK] = &sdm845_ipa.hw, > + [RPMH_CE_CLK] = &sdm845_ce.hw, > +}; > + > +static const struct clk_rpmh_desc clk_rpmh_sdm670 = { > + .clks = sdm670_rpmh_clocks, > + .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), > +}; > + > DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); > @@ -715,6 +735,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { > { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, > { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, > { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, > + { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, > { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, > { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, > { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, Reviewed-by: Neil Armstrong