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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT116.mail.protection.outlook.com (10.13.176.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5676.17 via Frontend Transport; Tue, 4 Oct 2022 11:05:00 +0000 Received: from [10.254.241.52] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 4 Oct 2022 06:04:56 -0500 Message-ID: Date: Tue, 4 Oct 2022 13:04:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH 1/2] dt-bindings: clk: Add binding for versal clocking wizard Content-Language: en-US To: Krzysztof Kozlowski , Rob Herring CC: Shubhrajyoti Datta , , , , , , , Greg Kroah-Hartman References: <20220930080400.15619-1-shubhrajyoti.datta@amd.com> <20220930080400.15619-2-shubhrajyoti.datta@amd.com> <20220930213924.GA1079711-robh@kernel.org> <6e58837e-896c-7069-7913-2afb90af5e95@amd.com> <57989d3e-a186-1d67-cff9-6a059f94ebd3@amd.com> <19bbea63-41d4-1b35-591e-1776eee1b2aa@linaro.org> <54652831-cdcc-7735-2b1b-66475ffce476@amd.com> From: Michal Simek In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 11:05:00.4774 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5f594f4-c846-49a1-7a8b-08daa5f84809 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5781 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 10/4/22 13:00, Krzysztof Kozlowski wrote: > On 03/10/2022 17:27, Michal Simek wrote: >>> >>> Exactly. The names xlnx,clocking-wizard and xlnx,clk-wizard-1.0 are >>> therefore not specific enough and mixing different devices. >> >> And just to be clear these IPs can be combined with systems where the main cpu >> can be Microblaze. I have also seen some vendors mixing RISC-V with Xilinx IPs. >> >> Please look below. >>> >>>> And because this is fpga world none is really describing programmable logic by >>>> hand because it would take a look a lot of time. That's why I created long time >>>> ago device-tree generator (DTG) which gets design data and based on it generate >>>> device tree description. Newest version is available for example here. >>>> https://github.com/Xilinx/device-tree-xlnx >>>> There is also newer version called system device tree generato >>>> https://github.com/Xilinx/system-device-tree-xlnx >>>> >>>> Because of this infrastructure user will all the time get proper compatible >>>> string which is aligned with IP catalog. >>> >>> I don't think so. Let's skip for now "clk" and "clocking" differences >>> and assume both are "clocking". You have then compatibles: >>> >>> xlnx,clocking-wizard and xlnx,clocking-wizard-1.0 >>> >>> and you said these are entirely different blocks. >>> >>> There is no way this creates readable DTS. >> >> And I really thank you for this discussion to do it properly and have proper >> compatible string and description for this block. >> >> Shubhrajyoti: please correct me if I am wrong. >> >> All Xilinx SOCs have programmable logic aligned with FPGAs. Zynq is based 28nm, >> ZynqMP (Ultrascale MPSOC) is based on 16nm and Versal is based on 7nm. >> >> I think these clocking IPs are using low level primitives available in PL logic. >> Which means there is connection to fpga/pl technology instead of SOC family and >> main cpu. > > Then maybe the compatibles (and device names) should have that fpga/pl > technology used to differentiate between them? I am already trying to find out better generic description without mentioning sizes. >> It can be of course said that if this is ZynqMP SOC that IP A is used. The same >> for Versal SOC. But for soft cores this can't be said. >> >> Would it be better to reflect PL technology in compatible string? > > Yes, although we might misunderstand what PL technology is. 28/16/7 nm > is the size of transistor or the process. Even two different processes > can use same type of technology, e.g. FinFET: > https://en.wikipedia.org/wiki/14_nm_process > https://en.wikipedia.org/wiki/10_nm_process > > You could have very similar (or even the same) designs done in 28 nm and > 16 nm. Does it mean these are entirely different devices? Not > necessarily... Maybe they are, maybe not, but is the size of process > differentiating? I actually don't know what's there in 28/16/7, I am > just saying that number alone might not mean different technology. > Programming API could be the same, inputs/outputs could be the same. > Just the size of transistor is different... I agree. Will try to come up with better name without nm inside to uniquely identify PL logic type. Thanks, Michal