From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@vger.kernel.org
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Paul Burton" <paulburton@kernel.org>,
"Paul Cercueil" <paul@crapouillou.net>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
hns@goldelico.com, paul@boddie.org.uk
Subject: Re: [PATCH v3 0/3] MIPS: CI20: Enable SMP with two CPUs
Date: Wed, 11 Nov 2026 21:00:47 -0800 [thread overview]
Message-ID: <e158710e-bf16-4010-8bf1-b8ee0ff2347b@gmail.com> (raw)
In-Reply-To: <20261112041422.2997275-1-f.fainelli@gmail.com>
On 11/11/2026 8:14 PM, Florian Fainelli wrote:
> This patch series resurrects SMP support for the CI20 board. This was
> submitted back in 2020 by Zhou Yanjie.
>
> Changes in v3:
>
> • Align the second line of the readl_poll_timeout_atomic() per Brian's
> feedback
> • Collected Paul's R-b and T-b tags
>
> Changes in v2:
>
> • Moved SMP sources to arch/mips/ingenic/ and the header to arch/mips/include/asm/
> • Removed CONFIG_MIPS_INGENIC_SMP, using CONFIG_MACH_JZ4780 and CONFIG_SMP directly
> • Renamed JZ4780-specific SMP symbols to XBurst names
> • Changed CPU enumeration to assign consecutive logical IDs and removed the explicit two-core limit
> • Changed mailbox IRQ allocation failure from panic to logging and returning
> • Shortened commit descriptions, removed Codex attribution, and adjusted source credits and sign-offs
> • Kept the clock polling patch and CI20 defconfig changes unchanged,
> added Paul's R-b for patch #1
> • Updated the kernel baseline to include additional upstream fixes
Looks like Sashiko found some issues to address, I will do that, re-test
and re-spin.
--
Florian
prev parent reply other threads:[~2026-11-12 5:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 4:14 [PATCH v3 0/3] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
2026-11-12 4:14 ` [PATCH v3 1/3] clk: ingenic: Poll JZ4780 CPU1 power status atomically Florian Fainelli
2026-11-12 4:14 ` [PATCH v3 2/3] MIPS: Ingenic: Add XBurst SMP support Florian Fainelli
2026-11-12 4:49 ` sashiko-bot
2026-11-12 4:14 ` [PATCH v3 3/3] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
2026-11-12 4:31 ` sashiko-bot
2026-11-12 5:00 ` Florian Fainelli [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e158710e-bf16-4010-8bf1-b8ee0ff2347b@gmail.com \
--to=f.fainelli@gmail.com \
--cc=bmasney+clk@redhat.com \
--cc=hns@goldelico.com \
--cc=jbrunet+clk@baylibre.com \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@vger.kernel.org \
--cc=paul@boddie.org.uk \
--cc=paul@crapouillou.net \
--cc=paulburton@kernel.org \
--cc=sboyd@kernel.org \
--cc=tsbogend@alpha.franken.de \
--cc=zhouyanjie@wanyeetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox