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Mon, 20 Oct 2025 12:35:36 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.151]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b65eb0362fbsm879008666b.39.2025.10.20.12.35.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Oct 2025 12:35:36 -0700 (PDT) Message-ID: Date: Mon, 20 Oct 2025 22:35:34 +0300 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 28/31] clk: at91: at91sam9260: switch to parent_hw and parent_data To: Ryan.Wanner@microchip.com, mturquette@baylibre.com, sboyd@kernel.org, alexandre.belloni@bootlin.com, nicolas.ferre@microchip.com Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, varshini.rajendran@microchip.com References: From: Claudiu Beznea Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Ryan, On 9/19/25 00:16, Ryan.Wanner@microchip.com wrote: > From: Claudiu Beznea > > Switch AT91SAM92600 clocks to use parent_hw and parent_data. Having > parent_hw instead of parent names improves to clock registration > speed and re-parenting. > > Signed-off-by: Claudiu Beznea > Signed-off-by: Ryan Wanner > --- > drivers/clk/at91/at91sam9260.c | 120 ++++++++++++++++++--------------- > 1 file changed, 67 insertions(+), 53 deletions(-) > > diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c > index 55350331b07e..2ac2a340da2f 100644 > --- a/drivers/clk/at91/at91sam9260.c > +++ b/drivers/clk/at91/at91sam9260.c > @@ -9,7 +9,7 @@ > > struct sck { > char *n; > - char *p; > + struct clk_hw *parent_hw; > u8 id; > }; > > @@ -24,7 +24,7 @@ struct at91sam926x_data { > const struct clk_pll_layout *pllb_layout; > const struct clk_pll_characteristics *pllb_characteristics; > const struct clk_master_characteristics *mck_characteristics; > - const struct sck *sck; > + struct sck *sck; > const struct pck *pck; > u8 num_sck; > u8 num_pck; > @@ -72,11 +72,11 @@ static const struct clk_pll_characteristics sam9260_pllb_characteristics = { > .out = sam9260_pllb_out, > }; > > -static const struct sck at91sam9260_systemck[] = { > - { .n = "uhpck", .p = "usbck", .id = 6 }, > - { .n = "udpck", .p = "usbck", .id = 7 }, > - { .n = "pck0", .p = "prog0", .id = 8 }, > - { .n = "pck1", .p = "prog1", .id = 9 }, > +static struct sck at91sam9260_systemck[] = { > + { .n = "uhpck", .id = 6 }, > + { .n = "udpck", .id = 7 }, > + { .n = "pck0", .id = 8 }, > + { .n = "pck1", .id = 9 }, > }; > > static const struct pck at91sam9260_periphck[] = { > @@ -213,15 +213,15 @@ static const struct clk_pll_characteristics sam9261_pllb_characteristics = { > .out = sam9261_pllb_out, > }; > > -static const struct sck at91sam9261_systemck[] = { > - { .n = "uhpck", .p = "usbck", .id = 6 }, > - { .n = "udpck", .p = "usbck", .id = 7 }, > - { .n = "pck0", .p = "prog0", .id = 8 }, > - { .n = "pck1", .p = "prog1", .id = 9 }, > - { .n = "pck2", .p = "prog2", .id = 10 }, > - { .n = "pck3", .p = "prog3", .id = 11 }, > - { .n = "hclk0", .p = "masterck_div", .id = 16 }, > - { .n = "hclk1", .p = "masterck_div", .id = 17 }, > +static struct sck at91sam9261_systemck[] = { > + { .n = "uhpck", .id = 6 }, > + { .n = "udpck", .id = 7 }, > + { .n = "pck0", .id = 8 }, > + { .n = "pck1", .id = 9 }, > + { .n = "pck2", .id = 10 }, > + { .n = "pck3", .id = 11 }, > + { .n = "hclk0", .id = 16 }, > + { .n = "hclk1", .id = 17 }, > }; > > static const struct pck at91sam9261_periphck[] = { > @@ -277,13 +277,13 @@ static const struct clk_pll_characteristics sam9263_pll_characteristics = { > .out = sam9260_plla_out, > }; > > -static const struct sck at91sam9263_systemck[] = { > - { .n = "uhpck", .p = "usbck", .id = 6 }, > - { .n = "udpck", .p = "usbck", .id = 7 }, > - { .n = "pck0", .p = "prog0", .id = 8 }, > - { .n = "pck1", .p = "prog1", .id = 9 }, > - { .n = "pck2", .p = "prog2", .id = 10 }, > - { .n = "pck3", .p = "prog3", .id = 11 }, > +static struct sck at91sam9263_systemck[] = { > + { .n = "uhpck", .id = 6 }, > + { .n = "udpck", .id = 7 }, > + { .n = "pck0", .id = 8 }, > + { .n = "pck1", .id = 9 }, > + { .n = "pck2", .id = 10 }, > + { .n = "pck3", .id = 11 }, > }; > > static const struct pck at91sam9263_periphck[] = { > @@ -330,12 +330,11 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, > struct at91sam926x_data *data) > { > const char *slowxtal_name, *mainxtal_name; > + struct clk_parent_data parent_data[4]; > struct pmc_data *at91sam9260_pmc; > u32 usb_div[] = { 1, 2, 4, 0 }; > - const char *parent_names[6]; > - const char *slck_name; > + struct clk_hw *usbck_hw, *hw; > struct regmap *regmap; > - struct clk_hw *hw; > int i; > bool bypass; > > @@ -363,12 +362,13 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, > > bypass = of_property_read_bool(np, "atmel,osc-bypass"); > > - hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, > + hw = at91_clk_register_main_osc(regmap, "main_osc", NULL, > + &AT91_CLK_PD_NAME(mainxtal_name), > bypass); > if (IS_ERR(hw)) > goto err_free; > > - hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); > + hw = at91_clk_register_rm9200_main(regmap, "mainck", NULL, &AT91_CLK_PD_HW(hw)); > if (IS_ERR(hw)) > goto err_free; > > @@ -382,20 +382,17 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, > if (IS_ERR(hw)) > goto err_free; > > - parent_names[0] = "slow_rc_osc"; > - parent_names[1] = "slow_xtal"; > - hw = at91_clk_register_sam9260_slow(regmap, "slck", > - parent_names, NULL, 2); > + parent_data[0] = AT91_CLK_PD_HW(hw); > + parent_data[1] = AT91_CLK_PD_NAME(slowxtal_name); > + hw = at91_clk_register_sam9260_slow(regmap, "slck", NULL, parent_data, 2); > if (IS_ERR(hw)) > goto err_free; > > at91sam9260_pmc->chws[PMC_SLOW] = hw; > - slck_name = "slck"; > - } else { > - slck_name = slowxtal_name; This section here should be kept.