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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acad99c4456sm25883766b.110.2025.04.11.02.15.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Apr 2025 02:15:09 -0700 (PDT) Message-ID: Date: Fri, 11 Apr 2025 11:15:06 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 15/18] arm64: dts: qcom: Add MXC power domain to videocc node on SM8650 To: Jagadeesh Kona , Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Vladimir Zapolskiy , Dmitry Baryshkov Cc: Ajit Pandey , Imran Shaik , Taniya Das , Satya Priya Kakitapalli , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Bryan O'Donoghue References: <20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com> <20250327-videocc-pll-multi-pd-voting-v3-15-895fafd62627@quicinc.com> <12986cda-99eb-4a1b-a97b-544ea01e2dbb@oss.qualcomm.com> <44dad3b5-ea3d-47db-8aca-8f67294fced9@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <44dad3b5-ea3d-47db-8aca-8f67294fced9@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ZwLrdvrtzWcwRStgRoIEYVkMsJ-CY6NU X-Authority-Analysis: v=2.4 cv=QuVe3Uyd c=1 sm=1 tr=0 ts=67f8dd9e cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=hak5HkhHT8-G3VIbWWkA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: ZwLrdvrtzWcwRStgRoIEYVkMsJ-CY6NU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_03,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110056 On 4/11/25 9:16 AM, Jagadeesh Kona wrote: > > > On 4/1/2025 8:57 PM, Konrad Dybcio wrote: >> On 3/27/25 10:52 AM, Jagadeesh Kona wrote: >>> Videocc requires both MMCX and MXC rails to be powered ON to configure >>> the video PLLs on SM8650 platform. Hence add MXC power domain to videocc >>> node on SM8650. >>> >>> Signed-off-by: Jagadeesh Kona >>> Reviewed-by: Dmitry Baryshkov >>> Reviewed-by: Bryan O'Donoghue >>> --- >>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- >>> 1 file changed, 2 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> index 818db6ba3b3be99c187512ea4acf2004422f6a18..ad60596b71d25bb0198b26660dc41195a1210a23 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >>> @@ -4959,7 +4959,8 @@ videocc: clock-controller@aaf0000 { >>> reg = <0 0x0aaf0000 0 0x10000>; >>> clocks = <&bi_tcxo_div2>, >>> <&gcc GCC_VIDEO_AHB_CLK>; >>> - power-domains = <&rpmhpd RPMHPD_MMCX>; >>> + power-domains = <&rpmhpd RPMHPD_MMCX>, >>> + <&rpmhpd RPMHPD_MXC>; >> >> So all other DTs touched in this series reference low_svs in required-opps >> >> Is that an actual requirement? Otherwise since Commit e3e56c050ab6 >> ("soc: qcom: rpmhpd: Make power_on actually enable the domain") we get the >> first nonzero state, which can be something like low_svs_d2 >> > Yes, commit e3e56c050ab6 enables the power-domain at first non-zero level, but in > some chipsets, the first nonzero state could be retention, which is not sufficient > for clock controller to operate. So required-opps is needed to ensure the rails are > at a level above retention for clock controller to operate. low_svs was choosen since > that is a level that is generally supported across all the chipsets, but low_svs_d2 > may not be supported on some chipsets. > > And required-opps is not mandatory for MXC power domain due to commit f0cc5f7cb43f > (pmdomain: qcom: rpmhpd: Skip retention level for Power Domains), which ensures MXC > always gets enabled above retention level. But it was added to make number of > required-opps uniform with the number of power domains based on discussion at [1]. > > [1]: https://lore.kernel.org/all/eoqqz5hyyq6ej5uo6phijbeu5qafbpfxlnreyzzcyfw23pl2yq@ftxnasc6sr2t/#t Alright, thanks for the explanation! Konrad