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On 2024/11/26 00:53, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Wed 20 Nov 2024 at 15:01, Xianwei Zhao via B4 Relay wrote: > >> From: Chuan Liu >> >> Add the peripherals clock controller dt-bindings for Amlogic A5 SoC family. >> >> Signed-off-by: Chuan Liu >> Reviewed-by: Rob Herring (Arm) >> Signed-off-by: Xianwei Zhao >> --- >> .../clock/amlogic,a5-peripherals-clkc.yaml | 130 ++++++++++++++++++++ >> .../clock/amlogic,a5-peripherals-clkc.h | 132 +++++++++++++++++++++ >> 2 files changed, 262 insertions(+) >> >> diff --git >> a/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml >> b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml >> new file mode 100644 >> index 000000000000..0f15e104fd12 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/amlogic,a5-peripherals-clkc.yaml >> @@ -0,0 +1,130 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/amlogic,a5-peripherals-clkc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Amlogic A5 series Peripheral Clock Controller >> + >> +maintainers: >> + - Xianwei Zhao >> + - Chuan Liu >> + >> +properties: >> + compatible: >> + const: amlogic,a5-peripherals-clkc >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + minItems: 18 >> + items: >> + - description: input oscillator (usually at 24MHz) >> + - description: input oscillators multiplexer >> + - description: input fix pll >> + - description: input fclk div 2 >> + - description: input fclk div 2p5 >> + - description: input fclk div 3 >> + - description: input fclk div 4 >> + - description: input fclk div 5 >> + - description: input fclk div 7 >> + - description: input mpll2 >> + - description: input mpll3 >> + - description: input gp0 pll >> + - description: input gp1 pll >> + - description: input hifi pll >> + - description: input sys clk >> + - description: input axi clk >> + - description: input sys pll div 16 >> + - description: input cpu clk div 16 >> + - description: input pad clock for rtc clk (optional) >> + - description: input ddr pll (optional) >> + - description: input source from clk-measure (optional) >> + >> + clock-names: >> + minItems: 18 >> + items: >> + - const: xtal_24m > > You should not mention the rate here. xtal is fine. > Will do. >> + - const: oscin >> + - const: fix >> + - const: fdiv2 >> + - const: fdiv2p5 >> + - const: fdiv3 >> + - const: fdiv4 >> + - const: fdiv5 >> + - const: fdiv7 >> + - const: mpll2 >> + - const: mpll3 >> + - const: gp0 >> + - const: gp1 >> + - const: hifi >> + - const: sysclk >> + - const: axiclk >> + - const: sysplldiv16 >> + - const: cpudiv16 >> + - const: pad_osc >> + - const: ddr >> + - const: clkmsr >> + >> + "#clock-cells": >> + const: 1 >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - "#clock-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + apb { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clock-controller@0 { >> + compatible = "amlogic,a5-peripherals-clkc"; >> + reg = <0x0 0x0 0x0 0x224>; >> + #clock-cells = <1>; >> + clocks = <&xtal_24m>, >> + <&scmi_clk 0>, >> + <&scmi_clk 7>, >> + <&scmi_clk 15>, >> + <&scmi_clk 17>, >> + <&scmi_clk 19>, >> + <&scmi_clk 21>, >> + <&scmi_clk 23>, >> + <&scmi_clk 25>, >> + <&clkc_pll 6>, >> + <&clkc_pll 8>, >> + <&clkc_pll 10>, >> + <&scmi_clk 5>, >> + <&clkc_pll 12>, >> + <&scmi_clk 1>, >> + <&scmi_clk 2>, >> + <&scmi_clk 9>, >> + <&scmi_clk 10>; >> + clock-names = "xtal_24m", >> + "oscin", >> + "fix", >> + "fdiv2", >> + "fdiv2p5", >> + "fdiv3", >> + "fdiv4", >> + "fdiv5", >> + "fdiv7", >> + "mpll2", >> + "mpll3", >> + "gp0", >> + "gp1", >> + "hifi", >> + "sysclk", >> + "axiclk", >> + "sysplldiv16", >> + "cpudiv16"; >> + }; >> + }; >> diff --git a/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h >> new file mode 100644 >> index 000000000000..74e740ebe6bd >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,a5-peripherals-clkc.h >> @@ -0,0 +1,132 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + * Author: Chuan Liu >> + */ >> + >> +#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H >> +#define _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H >> + >> +#define CLKID_RTC_XTAL_CLKIN 0 >> +#define CLKID_RTC_32K_DIV 1 >> +#define CLKID_RTC_32K_MUX 2 >> +#define CLKID_RTC_32K 3 >> +#define CLKID_RTC_CLK 4 >> +#define CLKID_SYS_RESET_CTRL 5 >> +#define CLKID_SYS_PWR_CTRL 6 >> +#define CLKID_SYS_PAD_CTRL 7 >> +#define CLKID_SYS_CTRL 8 >> +#define CLKID_SYS_TS_PLL 9 >> +#define CLKID_SYS_DEV_ARB 10 >> +#define CLKID_SYS_MAILBOX 11 >> +#define CLKID_SYS_JTAG_CTRL 12 >> +#define CLKID_SYS_IR_CTRL 13 >> +#define CLKID_SYS_MSR_CLK 14 >> +#define CLKID_SYS_ROM 15 >> +#define CLKID_SYS_CPU_ARB 16 >> +#define CLKID_SYS_RSA 17 >> +#define CLKID_SYS_SAR_ADC 18 >> +#define CLKID_SYS_STARTUP 19 >> +#define CLKID_SYS_SECURE 20 >> +#define CLKID_SYS_SPIFC 21 >> +#define CLKID_SYS_DSPA 22 >> +#define CLKID_SYS_NNA 23 >> +#define CLKID_SYS_ETH_MAC 24 >> +#define CLKID_SYS_RAMA 25 >> +#define CLKID_SYS_RAMB 26 >> +#define CLKID_SYS_AUDIO_TOP 27 >> +#define CLKID_SYS_AUDIO_VAD 28 >> +#define CLKID_SYS_USB 29 >> +#define CLKID_SYS_SD_EMMC_A 30 >> +#define CLKID_SYS_SD_EMMC_C 31 >> +#define CLKID_SYS_PWM_AB 32 >> +#define CLKID_SYS_PWM_CD 33 >> +#define CLKID_SYS_PWM_EF 34 >> +#define CLKID_SYS_PWM_GH 35 >> +#define CLKID_SYS_SPICC_1 36 >> +#define CLKID_SYS_SPICC_0 37 >> +#define CLKID_SYS_UART_A 38 >> +#define CLKID_SYS_UART_B 39 >> +#define CLKID_SYS_UART_C 40 >> +#define CLKID_SYS_UART_D 41 >> +#define CLKID_SYS_UART_E 42 >> +#define CLKID_SYS_I2C_M_A 43 >> +#define CLKID_SYS_I2C_M_B 44 >> +#define CLKID_SYS_I2C_M_C 45 >> +#define CLKID_SYS_I2C_M_D 46 >> +#define CLKID_SYS_RTC 47 >> +#define CLKID_AXI_AUDIO_VAD 48 >> +#define CLKID_AXI_AUDIO_TOP 49 >> +#define CLKID_AXI_RAMB 50 >> +#define CLKID_AXI_RAMA 51 >> +#define CLKID_AXI_NNA 52 >> +#define CLKID_AXI_DEV1_DMC 53 >> +#define CLKID_AXI_DEV0_DMC 54 >> +#define CLKID_AXI_DSP_DMC 55 >> +#define CLKID_12_24M_IN 56 >> +#define CLKID_12M_24M 57 >> +#define CLKID_FCLK_25M_DIV 58 >> +#define CLKID_FCLK_25M 59 >> +#define CLKID_GEN_SEL 60 >> +#define CLKID_GEN_DIV 61 >> +#define CLKID_GEN 62 >> +#define CLKID_SARADC_SEL 63 >> +#define CLKID_SARADC_DIV 64 >> +#define CLKID_SARADC 65 >> +#define CLKID_PWM_A_SEL 66 >> +#define CLKID_PWM_A_DIV 67 >> +#define CLKID_PWM_A 68 >> +#define CLKID_PWM_B_SEL 69 >> +#define CLKID_PWM_B_DIV 70 >> +#define CLKID_PWM_B 71 >> +#define CLKID_PWM_C_SEL 72 >> +#define CLKID_PWM_C_DIV 73 >> +#define CLKID_PWM_C 74 >> +#define CLKID_PWM_D_SEL 75 >> +#define CLKID_PWM_D_DIV 76 >> +#define CLKID_PWM_D 77 >> +#define CLKID_PWM_E_SEL 78 >> +#define CLKID_PWM_E_DIV 79 >> +#define CLKID_PWM_E 80 >> +#define CLKID_PWM_F_SEL 81 >> +#define CLKID_PWM_F_DIV 82 >> +#define CLKID_PWM_F 83 >> +#define CLKID_PWM_G_SEL 84 >> +#define CLKID_PWM_G_DIV 85 >> +#define CLKID_PWM_G 86 >> +#define CLKID_PWM_H_SEL 87 >> +#define CLKID_PWM_H_DIV 88 >> +#define CLKID_PWM_H 89 >> +#define CLKID_SPICC_0_SEL 90 >> +#define CLKID_SPICC_0_DIV 91 >> +#define CLKID_SPICC_0 92 >> +#define CLKID_SPICC_1_SEL 93 >> +#define CLKID_SPICC_1_DIV 94 >> +#define CLKID_SPICC_1 95 >> +#define CLKID_SD_EMMC_A_SEL 96 >> +#define CLKID_SD_EMMC_A_DIV 97 >> +#define CLKID_SD_EMMC_A 98 >> +#define CLKID_SD_EMMC_C_SEL 99 >> +#define CLKID_SD_EMMC_C_DIV 100 >> +#define CLKID_SD_EMMC_C 101 >> +#define CLKID_TS_DIV 102 >> +#define CLKID_TS 103 >> +#define CLKID_ETH_125M_DIV 104 >> +#define CLKID_ETH_125M 105 >> +#define CLKID_ETH_RMII_DIV 106 >> +#define CLKID_ETH_RMII 107 >> +#define CLKID_DSPA_0_SEL 108 >> +#define CLKID_DSPA_0_DIV 109 >> +#define CLKID_DSPA_0 110 >> +#define CLKID_DSPA_1_SEL 111 >> +#define CLKID_DSPA_1_DIV 112 >> +#define CLKID_DSPA_1 113 >> +#define CLKID_DSPA 114 >> +#define CLKID_NNA_CORE_SEL 115 >> +#define CLKID_NNA_CORE_DIV 116 >> +#define CLKID_NNA_CORE 117 >> +#define CLKID_NNA_AXI_SEL 118 >> +#define CLKID_NNA_AXI_DIV 119 >> +#define CLKID_NNA_AXI 120 >> + >> +#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_A5_PERIPHERALS_CLKC_H */ > > -- > Jerome