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[83.9.1.44]) by smtp.gmail.com with ESMTPSA id u22-20020ac258d6000000b004b52aea5ff8sm532076lfo.30.2022.12.17.07.15.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 17 Dec 2022 07:15:47 -0800 (PST) Message-ID: Date: Sat, 17 Dec 2022 16:15:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 12/15] clk: qcom: gcc-qcs404: add support for GDSCs Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> <20221217001730.540502-13-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20221217001730.540502-13-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 17.12.2022 01:17, Dmitry Baryshkov wrote: > Add support for two GDSCs provided by this clock controller. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/clk/qcom/gcc-qcs404.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c > index 8fb268671f0c..f8dbfffc2b8e 100644 > --- a/drivers/clk/qcom/gcc-qcs404.c > +++ b/drivers/clk/qcom/gcc-qcs404.c > @@ -19,6 +19,7 @@ > #include "clk-rcg.h" > #include "clk-regmap.h" > #include "common.h" > +#include "gdsc.h" > #include "reset.h" > > enum { > @@ -2598,6 +2599,22 @@ static struct clk_branch gcc_wdsp_q6ss_axim_clk = { > }, > }; > > +static struct gdsc mdss_gdsc = { > + .gdscr = 0x4d078, > + .pd = { > + .name = "mdss", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > +static struct gdsc oxili_gdsc = { > + .gdscr = 0x5901c, > + .pd = { > + .name = "oxili", > + }, > + .pwrsts = PWRSTS_OFF_ON, > +}; > + > static struct clk_hw *gcc_qcs404_hws[] = { > &cxo.hw, > }; > @@ -2748,6 +2765,11 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { > > }; > > +static struct gdsc *gcc_qcs404_gdscs[] = { > + [MDSS_GDSC] = &mdss_gdsc, > + [OXILI_GDSC] = &oxili_gdsc, > +}; > + > static const struct qcom_reset_map gcc_qcs404_resets[] = { > [GCC_GENI_IR_BCR] = { 0x0F000 }, > [GCC_CDSP_RESTART] = { 0x18000 }, > @@ -2790,6 +2812,8 @@ static const struct qcom_cc_desc gcc_qcs404_desc = { > .num_resets = ARRAY_SIZE(gcc_qcs404_resets), > .clk_hws = gcc_qcs404_hws, > .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws), > + .gdscs = gcc_qcs404_gdscs, > + .num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs), > }; > > static const struct of_device_id gcc_qcs404_match_table[] = {