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Tue, 23 Jan 2024 09:33:17 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40N9XGOZ014957 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Jan 2024 09:33:16 GMT Received: from [10.216.0.128] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 23 Jan 2024 01:33:11 -0800 Message-ID: Date: Tue, 23 Jan 2024 15:03:03 +0530 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH v6 01/12] clk: qcom: branch: Add a helper for setting the enable bit To: Konrad Dybcio , Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Marijn Suijten , , , , , Johan Hovold , Bryan O'Donoghue References: <20230717-topic-branch_aon_cleanup-v6-0-46d136a4e8d0@linaro.org> <20230717-topic-branch_aon_cleanup-v6-1-46d136a4e8d0@linaro.org> Content-Language: en-US From: Imran Shaik In-Reply-To: <20230717-topic-branch_aon_cleanup-v6-1-46d136a4e8d0@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -9zgUxEza7hK566H9pMD3G5V06JJNCFs X-Proofpoint-ORIG-GUID: -9zgUxEza7hK566H9pMD3G5V06JJNCFs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-23_04,2024-01-23_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 clxscore=1011 impostorscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401230069 On 1/13/2024 8:20 PM, Konrad Dybcio wrote: > We hardcode some clocks to be always-on, as they're essential to the > functioning of the SoC / some peripherals. Add a helper to do so > to make the writes less magic. > > Reviewed-by: Johan Hovold > Reviewed-by: Bryan O'Donoghue > Signed-off-by: Konrad Dybcio > --- > drivers/clk/qcom/clk-branch.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h > index 8ffed603c050..0514bc43100b 100644 > --- a/drivers/clk/qcom/clk-branch.h > +++ b/drivers/clk/qcom/clk-branch.h > @@ -64,6 +64,7 @@ struct clk_mem_branch { > #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) > #define CBCR_WAKEUP GENMASK(11, 8) > #define CBCR_SLEEP GENMASK(7, 4) > +#define CBCR_CLOCK_ENABLE BIT(0) > > static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, > struct clk_branch clk, bool on) > @@ -98,6 +99,12 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc > FIELD_PREP(CBCR_SLEEP, val)); > } > > +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) > +{ > + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, > + CBCR_CLOCK_ENABLE); > +} > + Could you please help me understand how this helper function is useful? Seems like this is just for reducing parameters compared to regmap_update_bits(). But anyhow the same is being done in the existing clock controller drivers with a comment which explains the functionality. Thanks & Regards, Imran > extern const struct clk_ops clk_branch_ops; > extern const struct clk_ops clk_branch2_ops; > extern const struct clk_ops clk_branch_simple_ops; >