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([2a01:e0a:982:cbb0:e5e5:892f:e81f:7cad]) by smtp.gmail.com with ESMTPSA id fc14-20020a05600c524e00b004161af729f4sm17228944wmb.31.2024.04.22.09.51.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Apr 2024 09:51:37 -0700 (PDT) Message-ID: Date: Mon, 22 Apr 2024 18:51:36 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v12 4/7] drm/meson: gate px_clk when setting rate To: Martin Blumenstingl Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jagan Teki , Nicolas Belin , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org References: <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-0-99ecdfdc87fc@linaro.org> <20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-4-99ecdfdc87fc@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Martin, On 10/04/2024 21:34, Martin Blumenstingl wrote: > Hi Neil, > > On Wed, Apr 3, 2024 at 9:46 AM Neil Armstrong wrote: >> >> Disable the px_clk when setting the rate to recover a fully >> configured and correctly reset VCLK clock tree after the rate >> is set. >> >> Fixes: 77d9e1e6b846 ("drm/meson: add support for MIPI-DSI transceiver") >> Signed-off-by: Neil Armstrong >> --- >> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c >> index a6bc1bdb3d0d..a10cff3ca1fe 100644 >> --- a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c >> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c >> @@ -95,6 +95,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data) >> return ret; >> } >> >> + clk_disable_unprepare(mipi_dsi->px_clk); > nit-pick: clk_disable(mipi_dsi->px_clk); should be enough here as my > understanding is that we only need to {un,}prepare a clock once. > >> ret = clk_set_rate(mipi_dsi->px_clk, mipi_dsi->mode->clock * 1000); >> >> if (ret) { >> @@ -103,6 +104,12 @@ static int dw_mipi_dsi_phy_init(void *priv_data) >> return ret; >> } >> >> + ret = clk_prepare_enable(mipi_dsi->px_clk); >> + if (ret) { >> + dev_err(mipi_dsi->dev, "Failed to enable DSI Pixel clock (ret %d)\n", ret); >> + return ret; > If we ever hit this error case then there will be a lot of additional > errors in the kernel log: > - initially the clock is prepared and enabled in > meson_dw_mipi_dsi_probe() by calling devm_clk_get_enabled() > - we then disable the clock above (generally disabling a clock is > expected to always succeed) > - if the clock can NOT be re-enabled here we just log the error > - in case a user tries to rmmod the driver (to modprobe it again) to > try and recover from an error the automatic disabling of the pix_clk > (based on devm_clk_get_enabled() where it was enabled initially) there > will be a splat because the clock is already disabled (and enabled > count is zero, so it cannot be disabled any further) > > For the 32-bit SoC video clocks I keep track of them being enabled or > disabled, see [0], [1] and [2]. > In my case this is important because we can run into cases where the > PLL doesn't lock (I am not sure how likely this is for your case). > > It *seems* like we need to do something similar as > dw_mipi_dsi_phy_init() can be called when changing the display > resolution (or whenever drm_bridge_funcs.atomic_pre_enable) is called. > To illustrate what I have in mind I attached a diff (it's based on > this patch) - it's compile tested only as I have no DSI hardware. > In case dw_mipi_dsi_phy_init() is called only once per device > lifecycle things may get easier. > > PS: I'm so happy that we don't need any clock notifiers for this! > So: good work with the clock driver bits. I checked and tested your patches and it doesn't work because the pc_clk needs to be disabled & prepared in order to correctly reset and setup again the video clock tree. dw_mipi_dsi_phy_init() is called at each DSI mode change, but it requires a full clock tree recalc and reset, so it's safer to keep the current design. I'll try to send a change to better handle the disable_unprepare() failure, but definitely only calling clk_disable() wasn't enough. Thanks, Neil > > > Let me know what you think, > Martin > > > [0] https://github.com/xdarklight/linux/blob/meson-mx-integration-6.9-20240323/drivers/gpu/drm/meson/meson_vclk.c#L1177-L1179 > [1] https://github.com/xdarklight/linux/blob/meson-mx-integration-6.9-20240323/drivers/gpu/drm/meson/meson_vclk.c#L1077 > [2] https://github.com/xdarklight/linux/blob/meson-mx-integration-6.9-20240323/drivers/gpu/drm/meson/meson_vclk.c#L1053