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Wed, 13 Sep 2023 03:32:29 GMT Received: from [10.216.41.52] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 12 Sep 2023 20:32:21 -0700 Message-ID: Date: Wed, 13 Sep 2023 09:02:13 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH V2 6/7] arm64: dts: qcom: ipq9574: Add support for nsscc node To: Dmitry Baryshkov CC: , , , , , , , , , , , , , , , , , , , , , , , References: <20230825091234.32713-1-quic_devipriy@quicinc.com> <20230825091234.32713-7-quic_devipriy@quicinc.com> Content-Language: en-US From: Devi Priya In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gApxFy5Cy_uY5wxT9JTOvWBqjExHH7f3 X-Proofpoint-ORIG-GUID: gApxFy5Cy_uY5wxT9JTOvWBqjExHH7f3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-12_24,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 clxscore=1015 spamscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 bulkscore=0 suspectscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309130027 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 8/25/2023 4:58 PM, Dmitry Baryshkov wrote: > On Fri, 25 Aug 2023 at 12:15, Devi Priya wrote: >> >> Add a node for the nss clock controller found on ipq9574 based devices. >> >> Signed-off-by: Devi Priya >> --- >> Changes in V2: >> - Dropped the fixed clock node gcc_gpll0_out_aux and added >> support for the same in gcc driver >> - Updated the node name to clock-controller@39b00000 >> - Added clock-names to retrieve the nssnoc clocks and add them >> to the list of pm clocks in nss driver >> >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 48 +++++++++++++++++++++++++++ >> 1 file changed, 48 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 51aba071c1eb..903311547e96 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -10,6 +10,8 @@ >> #include >> #include >> #include >> +#include >> +#include >> #include >> >> / { >> @@ -18,6 +20,24 @@ / { >> #size-cells = <2>; >> >> clocks { >> + bias_pll_cc_clk: bias-pll-cc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1200000000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <461500000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <353000000>; >> + #clock-cells = <0>; >> + }; > > Which part provides these clocks? The Bias PLL generates these clocks based on the reference clock. > >> + >> sleep_clk: sleep-clk { >> compatible = "fixed-clock"; >> #clock-cells = <0>; >> @@ -722,6 +742,34 @@ frame@b128000 { >> status = "disabled"; >> }; >> }; >> + >> + nsscc: clock-controller@39b00000 { >> + compatible = "qcom,ipq9574-nsscc"; >> + reg = <0x39b00000 0x80000>; >> + clocks = <&gcc GCC_NSSNOC_NSSCC_CLK>, >> + <&gcc GCC_NSSNOC_SNOC_CLK>, >> + <&gcc GCC_NSSNOC_SNOC_1_CLK>, >> + <&bias_pll_cc_clk>, >> + <&bias_pll_nss_noc_clk>, >> + <&bias_pll_ubi_nc_clk>, >> + <&gcc GPLL0_OUT_AUX>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <0>, >> + <&xo_board_clk>; > > If you move xo_board closer to the start of the list, it will be > slightly easier to review. Sure okay > >> + clock-names = "nssnoc_nsscc", "nssnoc_snoc", "nssnoc_snoc_1", >> + "bias_pll_cc_clk", "bias_pll_nss_noc_clk", >> + "bias_pll_ubi_nc_clk", "gpll0_out_aux", "uniphy0_nss_rx_clk", >> + "uniphy0_nss_tx_clk", "uniphy1_nss_rx_clk", >> + "uniphy1_nss_tx_clk", "uniphy2_nss_rx_clk", >> + "uniphy2_nss_tx_clk", "xo_board_clk"; > > You are using clock indices. Please drop clock-names. Sure okay Thanks, Devi Priya > >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> }; >> >> thermal-zones { >> -- >> 2.34.1 >> > >