From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Luo Jie <quic_luoj@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
p.zabel@pengutronix.de
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
quic_srichara@quicinc.com
Subject: Re: [PATCH 2/3] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
Date: Mon, 7 Aug 2023 08:52:08 +0200 [thread overview]
Message-ID: <ef996a7e-6eba-4366-c3ea-0d08f2768e98@linaro.org> (raw)
In-Reply-To: <20230801085352.22873-3-quic_luoj@quicinc.com>
On 01/08/2023 10:53, Luo Jie wrote:
> QCA8386/QCA8084 includes the clock & reset controller that is
> accessed by MDIO bus. Two work modes are supported, qca8386 works
> as switch mode, qca8084 works as PHY mode.
>
> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
> ---
> .../bindings/clock/qcom,nsscc-qca8k.yaml | 59 ++++++++++
> include/dt-bindings/clock/qcom,nsscc-qca8k.h | 102 ++++++++++++++++++
> include/dt-bindings/reset/qcom,nsscc-qca8k.h | 76 +++++++++++++
> 3 files changed, 237 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
> create mode 100644 include/dt-bindings/clock/qcom,nsscc-qca8k.h
> create mode 100644 include/dt-bindings/reset/qcom,nsscc-qca8k.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
> new file mode 100644
> index 000000000000..8fb77156070c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,nsscc-qca8k.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,nsscc-qca8k.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
> +
> +maintainers:
> + - Luo Jie <quic_luoj@quicinc.com>
> +
> +description: |
> + Qualcomm NSS clock control module provides the clocks and resets
> + on QCA8386(switch mode)/QCA8084(PHY mode)
> +
> + See also::
> + include/dt-bindings/clock/qcom,nsscc-qca8k.h
> + include/dt-bindings/reset/qcom,nsscc-qca8k.h
> +
> +properties:
> + compatible:
> + const: qcom,nsscc-qca8k
SoC name is before IP block names. See:
Documentation/devicetree/bindings/arm/qcom-soc.yaml
qca8k is not SoC specific. I don't know what you are documenting here,
but if this is a SoC, then follow SoC rules.
If this is not SoC, it confuses me a bit to use GCC binding.
Anyway, this was not tested, as pointed out by bot... Please test the
code before sending.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-08-07 6:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-01 8:53 [PATCH 0/3] add clock controller of qca8386/qca8084 Luo Jie
2023-08-01 8:53 ` [PATCH 1/3] clk: Add the flag CLK_ENABLE_MUTEX_LOCK of enabling clock Luo Jie
2023-08-01 19:18 ` Stephen Boyd
2023-08-02 10:33 ` Jie Luo
2023-08-01 8:53 ` [PATCH 2/3] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions Luo Jie
2023-08-01 9:36 ` Rob Herring
2023-08-07 6:52 ` Krzysztof Kozlowski [this message]
2023-08-08 5:19 ` Jie Luo
2023-08-08 5:57 ` Krzysztof Kozlowski
2023-08-08 6:31 ` Jie Luo
2023-08-08 6:46 ` Krzysztof Kozlowski
2023-08-08 6:59 ` Jie Luo
2023-08-01 8:53 ` [PATCH 3/3] clk: qcom: add clock controller driver for qca8386/qca8084 Luo Jie
2023-08-01 19:16 ` Randy Dunlap
2023-08-02 10:34 ` Jie Luo
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