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[95.49.125.236]) by smtp.gmail.com with ESMTPSA id p8-20020a2eba08000000b002776eb5b1ccsm1546978lja.4.2022.11.29.05.23.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Nov 2022 05:23:59 -0800 (PST) Message-ID: Date: Tue, 29 Nov 2022 14:23:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH 1/4] clk: qcom: rpmh: group clock definitions together Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder References: <20221129101025.960110-1-dmitry.baryshkov@linaro.org> <20221129101025.960110-2-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20221129101025.960110-2-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 29.11.2022 11:10, Dmitry Baryshkov wrote: > In preparations to the further changes, group all RPMH clock definitions > to ease review. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/clk/qcom/clk-rpmh.c | 55 ++++++++++++++++++------------------- > 1 file changed, 26 insertions(+), 29 deletions(-) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index 1da45a6e2f29..f13c9bd610d0 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -342,19 +342,45 @@ static const struct clk_ops clk_rpmh_bcm_ops = { > }; > > /* Resource name must match resource id present in cmd-db */ > +DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); > DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2); > +DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); > +DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); > + > +DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); > DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2); > DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); > +DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); > + > +DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); > +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); > +DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); > + > +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4); > +DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); > + > DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1); > DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1); > DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1); > DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1); > +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); > +DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); > + > DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1); > DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1); > +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > + > +DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); > + > DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0"); > DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0"); > +DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); > +DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); > +DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); > +DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); > > static struct clk_hw *sdm845_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > @@ -398,11 +424,6 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = { > .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > -DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > -DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); > -DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0"); > - > static struct clk_hw *sdx55_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > @@ -478,8 +499,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = { > .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); > - > static struct clk_hw *sm8250_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > @@ -500,12 +519,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { > .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2); > -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1); > -DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1); > -DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0"); > -DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0"); > - > static struct clk_hw *sm8350_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > @@ -533,8 +546,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { > .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); > - > static struct clk_hw *sc8280xp_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > @@ -550,12 +561,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { > .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), > }; > > -/* Resource name must match resource id present in cmd-db */ > -DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); > - > -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); > -DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4); > - > static struct clk_hw *sm8450_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, > @@ -600,10 +605,6 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = { > .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4); > -DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4); > -DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4); > - > static struct clk_hw *sm6350_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, > @@ -620,8 +621,6 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = { > .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4); > - > static struct clk_hw *sdx65_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw, > @@ -644,8 +643,6 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = { > .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), > }; > > -DEFINE_CLK_RPMH_ARC(qdu1000, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 1); > - > static struct clk_hw *qdu1000_rpmh_clocks[] = { > [RPMH_CXO_CLK] = &qdu1000_bi_tcxo.hw, > [RPMH_CXO_CLK_A] = &qdu1000_bi_tcxo_ao.hw,