From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller To: Dmitry Osipenko , Stephen Warren , Thierry Reding , "Laxman Dewangan" , Peter De Schrijver , Prashant Gaikwad , "Michael Turquette" , Stephen Boyd , "Rob Herring" , Vinod Koul CC: , , , , References: <604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com> <96bfdacb-3d2d-66b6-70f7-a87664b1afc7@gmail.com> <0fd316e9-3584-e9bd-2a8b-e73eaa6a9a48@nvidia.com> <9e4e3dc1-85cd-2096-118c-7d0c929b9246@wwwdotorg.org> <5a5ce745-750f-9c8f-5129-c9b0f7aee614@gmail.com> <788f73dc-e011-aa9d-8850-f01ab9459c91@wwwdotorg.org> <795e4b19-b747-74c1-6f92-b961ab4bf822@gmail.com> <4443a8fb-7a4d-922b-2dd3-53236d39a050@nvidia.com> From: Jon Hunter Message-ID: Date: Tue, 3 Oct 2017 13:19:31 +0100 MIME-Version: 1.0 In-Reply-To: Return-Path: jonathanh@nvidia.com Content-Type: text/plain; charset="utf-8" List-ID: On 03/10/17 13:07, Dmitry Osipenko wrote: > On 03.10.2017 13:32, Jon Hunter wrote: >> >> >> On 03/10/17 00:02, Dmitry Osipenko wrote: >>> On 02.10.2017 20:05, Stephen Warren wrote: >>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote: >>>>> On 29.09.2017 22:30, Stephen Warren wrote: >>>>>> On 09/27/2017 02:34 AM, Jon Hunter wrote: >>>>>>> >>>>>>> On 27/09/17 02:57, Dmitry Osipenko wrote: >>>>>>>> On 26.09.2017 17:50, Jon Hunter wrote: >>>>>>>>> >>>>>>>>> On 26/09/17 00:22, Dmitry Osipenko wrote: >>>>>>>>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that pr= esents >>>>>>>>>> on Tegra20/30 SoC's. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Dmitry Osipenko >>>>>>>>>> --- >>>>>>>>>> =C2=A0=C2=A0 .../bindings/dma/nvidia,tegra20-ahbdma.txt=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 23 >>>>>>>>>> ++++++++++++++++++++++ >>>>>>>>>> =C2=A0=C2=A0 1 file changed, 23 insertions(+) >>>>>>>>>> =C2=A0=C2=A0 create mode 100644 >>>>>>>>>> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt >>>>>>>>>> >>>>>>>>>> diff --git >>>>>>>>>> a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.tx= t >>>>>>>>>> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.tx= t >>>>>>>>>> new file mode 100644 >>>>>>>>>> index 000000000000..2af9aa76ae11 >>>>>>>>>> --- /dev/null >>>>>>>>>> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdm= a.txt >>>>>>>>>> @@ -0,0 +1,23 @@ >>>>>>>>>> +* NVIDIA Tegra AHB DMA controller >>>>>>>>>> + >>>>>>>>>> +Required properties: >>>>>>>>>> +- compatible:=C2=A0=C2=A0=C2=A0 Must be "nvidia,tegra20-ahbdma" >>>>>>>>>> +- reg:=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Should contain= registers base address and length. >>>>>>>>>> +- interrupts:=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA c= ontroller interrupt. >>>>>>>>>> +- clocks:=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA contr= oller clock. >>>>>>>>>> +- resets :=C2=A0=C2=A0=C2=A0 Should contain one entry, DMA cont= roller reset. >>>>>>>>>> +- #dma-cells:=C2=A0=C2=A0=C2=A0 Should be <1>. The cell represe= nts DMA request select >>>>>>>>>> value >>>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for the peripheral. = For more details consult the Tegra TRM's >>>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 documentation, in pa= rticular AHB DMA channel control register >>>>>>>>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQ_SEL field. >>>>>>>>> >>>>>>>>> What about the TRIG_SEL field? Do we need to handle this here as = well? >>>>>>>>> >>>>>>>> >>>>>>>> Actually, DMA transfer trigger isn't related a hardware descriptio= n. It's >>>>>>>> up to >>>>>>>> software to decide what trigger to select. So it shouldn't be in t= he binding. >>>>>>> >>>>>>> I think it could be, if say a board wanted a GPIO to trigger a tran= sfer. >>>>>>> >>>>>>>> And I think the same applies to requester... any objections? >>>>>>> >>>>>>> Well, the REQ_SEL should definitely be in the binding. >>>>>>> >>>>>>> Laxman, Stephen, what are your thoughts on the TRIG_SEL field? Look= s >>>>>>> like we never bothered with it for the APB DMA and so maybe no ones= uses >>>>>>> this. >>>>>> >>>>>> I don't think TRIG_SEL should be in the binding, at least at present= . While >>>>>> TRIG_SEL certainly is something used to configure the transfer, I be= lieve the >>>>>> semantics of the current DMA binding only cover DMA transfers that a= re initiated >>>>>> when SW desires, rather than being a combination of after SW program= s the >>>>>> transfer plus some other HW event. So, we always use a default/hard-= coded >>>>>> TRIG_SEL value. As such, there's no need for a TRIG_SEL value in DT.= There's >>>>>> certainly no known use-case that requires a non-default TRIG_SEL val= ue at >>>>>> present. We could add an extra #dma-cells value later if we find a u= se for it, >>>>>> and the semantics of that use-case make sense to add it to the DMA s= pecifier, >>>>>> rather than some other separate higher-level property/driver/... >>>>> >>>>> Thank you for the comment. If we'd want to extend the binding further= with the >>>>> trigger, how to differentiate trigger from the requester in a case of= a single >>>>> #data-cell? >>>>> >>>>> Of course realistically a chance that the further extension would be = needed is >>>>> very-very low, so we may defer the efforts to solve that question and= for now >>>>> make driver aware of the potential #dma-cells extension. >>>> >>>> The request selector cell isn't optional, so is always present. If we = later add >>>> an optional trig_sel cell, we'll either have: >>>> >>>> #dma-cells=3D<1>: req_sel >>>> >>>> or: >>>> >>>> #dma-cells=3D<2>: req_sel, trig_sel >>> >>> Why request sel. couldn't be optional? Could you please elaborate a bit= more? >>> >>> I think possible options are: >>> >>> #dma-cells=3D<1>: req_sel >>> #dma-cells=3D<1>: trig_sel >> >> With the above, how would you know that it is the req_sel or trig_sel >> that is specified? >> >>> #dma-cells=3D<2>: req_sel, trig_sel >>> >>> The only difference between request and trigger is that trigger issues = the whole >>> transfer, while request only a single burst. Isn't it possible to have = a case in >>> HW for the "trigger-only" option? If not or it's a rareness, then I agr= ee that >>> REQ_SEL must be mandatory. >> >> I think that what Stephen is proposing is that for now we go with >> '#dma-cells=3D<1>' and if we ever need to support the trigger cell we >> could add support for '#dma-cells=3D<2>'. So with this proposal the >> 'req_sel' would always be required for both '#dma-cells=3D<1>' and >> '#dma-cells=3D<2>'. Even if the req_sel is not actually used but the >> 'trig_sel' is, the user would have to set 'req_sel' to some pre-defined >> value (eg. -1) where we know to ignore it. >> >=20 > Okay, I see now. Thank you for the clarification, but then we should have= that > pre-defined value declared in the binding? I would have thought it should be in the dt-binding header. Cheers Jon --=20 nvpublic