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Fri, 25 Sep 2026 05:17:27 -0700 (PDT) X-Received: by 2002:a05:620a:370d:b0:93a:14c:329c with SMTP id af79cd13be357-93c43b93796mr401945985a.1.1790338646907; Fri, 25 Sep 2026 05:17:26 -0700 (PDT) Received: from [192.168.202.12] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2ae7357c17sm106318666b.13.2026.09.25.05.17.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Sep 2026 05:17:26 -0700 (PDT) Message-ID: Date: Fri, 25 Sep 2026 14:17:23 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: gcc: Fix GPLL enable register offset for Nord SoC To: Taniya Das , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Bartosz Golaszewski , Shawn Guo Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI1MDA0OCBTYWx0ZWRfX2l23V44hKEHl kfztTEU7ItyYTrHo5sqT+3istm2hW9xAG92QKdB+9hOII0NV9t8Jl1Y5qxPV+fqlkAqrx1pB2Zt AgZWUKsRaKklyowKa7cfIuNrWk4dsD/uQenA5jgW0vv8zKwoBGJ5tcVwc11j8trZmmiTQtw3+F9 OxiqeFXD8SQm1mE4dIgOWB6C2iH1Ca5gPGVeJ+8/7NPcqGDg9yJfEaGZXjY+SMykvygd487apnt jtemr0CpubdB3Rws4VWwdgYAs6eL7jWApJK0htE+0R61fLT/1ZaVyDfhtRY4Zj2vltA3WHenUVz hFNCwferxQKbZdPXKL9DS72TzbbiaRmKgrGzrIyTAClnIfgIaYoEsDv9JYWKUMbiRrfu6TlKbEt HMX7Zk/B+ah79kJfUvPcet3GOFJgeGbQQaol05QFXo1t5Yjz1ta/D4peYUdCuJUE8LGrqtVpXL0 jDNGR4Z9XOOUnZhe46g== X-Authority-Analysis: v=2.4 cv=ZfKIpcVA c=1 sm=1 tr=0 ts=6ab66657 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=7o7Fz_jXMTEYJjNRgMcA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: 2YP-7haN9lN5pxT2RvSI6xylJDHLldlP X-Proofpoint-GUID: 2YP-7haN9lN5pxT2RvSI6xylJDHLldlP X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI1MDA0OCBTYWx0ZWRfX5IXs/PW/DKpb BeYJDQaycwzZ4b5ZU34K2WIGaxNFjDYJv1jsa28vB5/o0V6oG1gt2P0z6wMNJkiqerbgGuM8uIy LxTCUb7JNKgy30mJqHSSX+D26lASr/Q= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-25_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609250048 On 9/24/26 11:39 AM, Taniya Das wrote: > The GPLLs in the North-East, North-West and South-East global clock > controllers on the Qualcomm Nord SoC were registered with a placeholder > enable register offset of 0x0. As a result the shared PLL voting register > was never programmed, leaving the PLLs' enable state uncontrolled. > > Point each GPLL at its actual GPLL_ENABLE register (0x57010 for the > North-East and South-East controllers, 0x76008 for the North-West > controller). Each PLL continues to select its own vote bit through > enable_mask. > > Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") > Signed-off-by: Taniya Das > --- Reviewed-by: Konrad Dybcio Konrad