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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af635a62acfsm417921466b.66.2025.07.28.05.15.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jul 2025 05:15:31 -0700 (PDT) Message-ID: Date: Mon, 28 Jul 2025 14:15:28 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks To: Krzysztof Kozlowski , Konrad Dybcio Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com> <20250723-topic-8750_gpucc-v2-1-56c93b84c390@oss.qualcomm.com> <20250724-blazing-therapeutic-python-1e96ca@kuoka> <54b617c1-bd1b-4244-b75d-57eaaa2c083d@oss.qualcomm.com> <5b8d42d5-d034-4495-9d28-27478a606d62@kernel.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 1Averh8o2og1ZZ-gHCENtNMFdnQN5UcN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI4MDA4NyBTYWx0ZWRfX1GpfoybKuO/P fyIUaWuSO72dSog9YsaFPKowNxFhiE9KPTVuQIzJ1tawWMdFqYdVAbocHO7RP8p3ImPm0hfjjm8 YaggEwCnu5tSkgPbYQwB2Ue6JYLqknFy/FznnYeVj/XEPxzIOTUP7gW+7q06ulvaQ8TCSvi+n2q bJPS5E8ensMY0E8sHA8npViq/KG0rZJt0Oxhn5cTyVbHv/2VXWaro7Muod4r4qeplfoMsorcXyT Z+Bwmf6wlZbr287t6+j83oJSzWYhyM5v9pt+LM20lrwSbubXsfixlEiCUrwIEGJfrhRKz+MyuO8 wXY2tQJdjpHPdWNSKJmvHehLOacuuulnlIGrWhosdOlhJflcmvt6CDOpvT+GtgAA+UPNLKwIV1p tcSoJDx/vcBOOLFHD/ktkhryGSBlrHkC78k/UnGlTohm203PwjRXd19A4VKe0oLpIP3ObHX/ X-Authority-Analysis: v=2.4 cv=DIWP4zNb c=1 sm=1 tr=0 ts=688769e6 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=WpjJ9PWMYFXYRfV5F1YA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: 1Averh8o2og1ZZ-gHCENtNMFdnQN5UcN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-28_03,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507280087 On 7/28/25 1:02 PM, Konrad Dybcio wrote: > On 7/28/25 7:01 AM, Krzysztof Kozlowski wrote: >> On 25/07/2025 11:30, Konrad Dybcio wrote: >>>>> >>>>> @@ -40,6 +42,9 @@ properties: >>>>> - description: GPLL0 main branch source >>>>> - description: GPLL0 div branch source >>>>> >>>>> + power-domains: >>>>> + maxItems: 1 >>>> >>>> This should be a different binding or you need to restrict other >>>> variants here. >>> >>> Actually looks like this is the same case as the recent videocc changes >>> (15 year old technical debt catching up to us..) >>> >>> I'll send a mass-fixup for this. >>> >>> Some platforms require 2 and some require 3 entries here. Do I have to >>> restrict them very specifically, or can I do: >>> >>> power-domains: >>> description: >>> Power domains required for the clock controller to operate >>> minItems: 2 >>> items: >>> - description: CX power domain >>> - description: MX power domain >>> - description: MXC power domain >>> >>> ? >> >> This is correct and should be in top level, but you still need to >> restrict them per each variant (minItems: 3 or maxItems: 2). > > So I was happy about how simple it was, until I realized we also need > to poke the VDD_GFX domain. It does however not necessarily exist on > all platforms and I don't want the binding to become a spaghetti of ifs.. > > CX & MX is present on all(?) platforms > GFX & MXC's (any combination of those, unfortunately) presence varies > > Is there anything better I can do than creating a separate case for: > > * CX_MX > * CX_MX_GFX > * CX_MX_MXC > * CX_MX_GFX_MXC Doesn't seem like it, turned out this wasn't as terrible a mess as I had imagined.. Konrad