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([2a01:e0a:982:cbb0:b623:41fc:e293:c9b1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ecf027b94sm1171556f8f.2.2024.10.18.00.26.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Oct 2024 00:26:44 -0700 (PDT) Message-ID: Date: Fri, 18 Oct 2024 09:26:43 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 13/14] clk: qcom: dispcc-sm8550: enable support for SAR2130P To: Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241017-sar2130p-clocks-v1-0-f75e740f0a8d@linaro.org> <20241017-sar2130p-clocks-v1-13-f75e740f0a8d@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20241017-sar2130p-clocks-v1-13-f75e740f0a8d@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/10/2024 18:57, Dmitry Baryshkov wrote: > The display clock controller on SAR2130P is very close to the clock > controller on SM8550 (and SM8650). Reuse existing driver to add support > for the controller on SAR2130P. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/Kconfig | 4 ++-- > drivers/clk/qcom/dispcc-sm8550.c | 18 ++++++++++++++++-- > 2 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 5f7bf9db76cfcef1ab18a6ba09fb4dc506695f9d..f314f26fe136c0fc1612edc0cca23c4deba5cd9f 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -968,10 +968,10 @@ config SM_DISPCC_8450 > config SM_DISPCC_8550 > tristate "SM8550 Display Clock Controller" > depends on ARM64 || COMPILE_TEST > - depends on SM_GCC_8550 || SM_GCC_8650 > + depends on SM_GCC_8550 || SM_GCC_8650 || SAR_GCC_2130P > help > Support for the display clock controller on Qualcomm Technologies, Inc > - SM8550 or SM8650 devices. > + SAR2130P, SM8550 or SM8650 devices. > Say Y if you want to support display devices and functionality such as > splash screen. > > diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c > index 7f9021ca0ecb0ef743a40bed1bb3d2cbcfa23dc7..e41d4104d77021cae6438886bcb7015469d86a9f 100644 > --- a/drivers/clk/qcom/dispcc-sm8550.c > +++ b/drivers/clk/qcom/dispcc-sm8550.c > @@ -75,7 +75,7 @@ static struct pll_vco lucid_ole_vco[] = { > { 249600000, 2000000000, 0 }, > }; > > -static const struct alpha_pll_config disp_cc_pll0_config = { > +static struct alpha_pll_config disp_cc_pll0_config = { > .l = 0xd, > .alpha = 0x6492, > .config_ctl_val = 0x20485699, > @@ -106,7 +106,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { > }, > }; > > -static const struct alpha_pll_config disp_cc_pll1_config = { > +static struct alpha_pll_config disp_cc_pll1_config = { > .l = 0x1f, > .alpha = 0x4000, > .config_ctl_val = 0x20485699, > @@ -594,6 +594,13 @@ static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { > { } > }; > > +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = { > + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = { > F(19200000, P_BI_TCXO, 1, 0, 0), > F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), > @@ -1750,6 +1757,7 @@ static struct qcom_cc_desc disp_cc_sm8550_desc = { > }; > > static const struct of_device_id disp_cc_sm8550_match_table[] = { > + { .compatible = "qcom,sar2130p-dispcc" }, > { .compatible = "qcom,sm8550-dispcc" }, > { .compatible = "qcom,sm8650-dispcc" }, > { } > @@ -1780,6 +1788,12 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) > disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650; > disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = > &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { > + disp_cc_pll0_config.l = 0x1f; > + disp_cc_pll0_config.alpha = 0x4000; > + disp_cc_pll0_config.user_ctl_val = 0x1; > + disp_cc_pll1_config.user_ctl_val = 0x1; > + disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p; > } > > clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); > Reviewed-by: Neil Armstrong