From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71C0128EC; Fri, 25 Apr 2025 14:46:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745592406; cv=none; b=JN5qGqdLHhBCHlNXkbkpLOjDLbetLGmln4VQBqRUkRLQ7fzLBr7AzUC3gZjgcqEdZG+l9L6vMPorVRCV6vsxZ1yFS2WvRWMgG53UltzSJPuAt7jG/eSau9MblfDMFAHbFE3fMwGXB6G6Kb74Jl7KUFkPrQgQUp4p6VQGW01Onws= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745592406; c=relaxed/simple; bh=KHMe3OlGoGnWcRJInhRahIcJzYzyZrBrXPmSKdqnqVU=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=dUx3dp6j/hlkf8JFtk9xBcp5LGf84q3VK6I2FNAKsvf1c59bPvmugrQiN4gVg8tFqm7ZEQxPHKrUtSDKs9JrVVjK6dPrf8yHbM4ztgw4s0AYQxv3civbbpkY0Bf68dqgsfK80kyrQCeuejT0GvqdrLTyFxFFrvjqYaSpJtDkS6k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GZZyu96I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GZZyu96I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1492CC4CEE4; Fri, 25 Apr 2025 14:46:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745592405; bh=KHMe3OlGoGnWcRJInhRahIcJzYzyZrBrXPmSKdqnqVU=; h=Date:Subject:To:References:From:In-Reply-To:From; b=GZZyu96IMNdT1z0KhNQMJNel37QXrrRT2E18XI6r5HmIC5hmAImGK8Pp2um1bZCdd VdffQwW8aPOA4Qc+dlGKODCGamFqfxtM+Gomc0J49kJzKFlxfOCAsT8/wp/JzazdX2 rJcCug3m1JSCmRNuzOpMPFUE/6BCR39HPTzqd4FDsJ3xH3Z1KKtG97vNlYaZQ2DxTw gJedKQHg7jYdGNwtLMwAMAcb1g57S5zUBw0gpizufJdwELCa8mnaBLkIYoI4kiT2St y3I4Ad5Z6HsIFvqui9Ni9zWCrHPjBLN0Bm0TR4TDlF6T2hyzjaVzodbjYbl60b+cx3 5H96lN2rKkmrA== Message-ID: Date: Fri, 25 Apr 2025 16:46:41 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 02/10] ARM: dts: exynos: Add rtc clock definitions for MAX77686 PMIC for Exynos4412 Odroid To: Anand Moon , Chanwoo Choi , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alim Akhtar , "open list:MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BO..." , "open list:COMMON CLK FRAMEWORK" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES" , "open list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES" References: <20250425132727.5160-1-linux.amoon@gmail.com> <20250425132727.5160-3-linux.amoon@gmail.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/04/2025 15:26, Anand Moon wrote: > The MAX77686A includes a crystal driver with an external load capacitance. > When enabled, the crystal driver starts in low power mode. The > LowJitterMode bit controls the crystal driver, allowing it to switch > between low power mode and low jitter mode (high power mode). > Setting the LowJitterMode bit to 1 activates low jitter mode on > three channels simultaneously. These three 32khz buffer outputs > (32KHAP, 32KHCP, P32KH) are independently enabled/disabled over I2C. > > The 32khz_ap output is typically routed to the AP Processor, while the > 32khz_cp and 32khz_pmic outputs are intended for BT, WLAN, BB, > or peripheral chipsets. > > Signed-off-by: Anand Moon > --- > arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi > index 93ddbd4b0a18..03943c666d11 100644 > --- a/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi > +++ b/arch/arm/boot/dts/samsung/exynos4412-odroid-common.dtsi > @@ -289,6 +289,13 @@ max77686: pmic@9 { > reg = <0x09>; > #clock-cells = <1>; > > + max77686_osc: clocks { > + compatible = "max77686-rtc"; I don't believe this works. Best regards, Krzysztof