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[79.139.233.37]) by smtp.googlemail.com with ESMTPSA id x4sm401012ljb.66.2020.01.07.15.21.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jan 2020 15:21:14 -0800 (PST) Subject: Re: [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20191218184407.25790-1-digetx@gmail.com> <20191218184407.25790-2-digetx@gmail.com> Message-ID: Date: Wed, 8 Jan 2020 02:21:13 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.3.0 MIME-Version: 1.0 In-Reply-To: <20191218184407.25790-2-digetx@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org 18.12.2019 21:44, Dmitry Osipenko пишет: > Both Tegra20 and Tegra30 are initializing display's parent clock > incorrectly because PLLP is running at 216/408MHz while display rate is > set to 600MHz, but pre-setting the parent isn't needed at all because > display driver selects proper parent anyways. > > Signed-off-by: Dmitry Osipenko > --- > drivers/clk/tegra/clk-tegra20.c | 2 -- > drivers/clk/tegra/clk-tegra30.c | 2 -- > 2 files changed, 4 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c > index 4d8222f5c638..0c14fb570343 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -1046,8 +1046,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { > { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, > { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, > { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, > - { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 }, > - { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 }, > { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, > diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c > index c8bc18e4d7e5..bd4d42005897 100644 > --- a/drivers/clk/tegra/clk-tegra30.c > +++ b/drivers/clk/tegra/clk-tegra30.c > @@ -1251,8 +1251,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { > { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, > { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, > { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, > - { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, > - { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, > { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, > { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, > { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, > Hello people, Could anyone please take a look at these trivial patches and give an ACK? Thanks in advance!