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(119.65.249.123) by 192.168.10.159 with ESMTP; 21 Jul 2025 13:31:52 +0900 X-Original-SENDERIP: 119.65.249.123 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: hgkim05@coasia.com X-Original-RCPTTO: krzk@kernel.org, ksk4725@coasia.com, jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Message-ID: Subject: Re: [PATCH 02/16] dt-bindings: clock: Add ARTPEC-8 CMU bindings From: Hakyeong Kim To: Krzysztof Kozlowski , ksk4725@coasia.com, Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Date: Mon, 21 Jul 2025 13:31:53 +0900 In-Reply-To: <7b9a8203-2d66-4735-a6a2-762f57fb5cef@kernel.org> References: <20250710002047.1573841-1-ksk4725@coasia.com> <20250710002047.1573841-3-ksk4725@coasia.com> <7b9a8203-2d66-4735-a6a2-762f57fb5cef@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4-0ubuntu2 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-07-10 at 09:10 +0200, Krzysztof Kozlowski wrote: > On 10/07/2025 02:20, ksk4725@coasia.com=C2=A0wrote: > > From: Hakyeong Kim > >=20 > > Add dt-schema for ARTPEC-8 SoC clock controller. > >=20 > > Add device-tree binding definitions for following CMU blocks: > > - CMU_CMU > > - CMU_BUS > > - CMU_CORE > > - CMU_CPUCL > > - CMU_FSYS > > - CMU_IMEM > > - CMU_PERI > >=20 > > Signed-off-by: Ravi Patel > > Signed-off-by: Hakyeong Kim >=20 > Confusing order, unless you really understand this, but considering > you > did not add your own SoB I claim you do not understand this. What > does > Ravi's SoB mean here? Ok, I will update the SoB section in all the patches. >=20 > > --- > > =C2=A0.../bindings/clock/axis,artpec8-clock.yaml=C2=A0=C2=A0=C2=A0 | 22= 4 > > ++++++++++++++++++ > > =C2=A01 file changed, 224 insertions(+) > > =C2=A0create mode 100644 > > Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml > >=20 > > diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8- > > clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec8- > > clock.yaml > > new file mode 100644 > > index 000000000000..baacea10599b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/axis,artpec8- > > clock.yaml > > @@ -0,0 +1,224 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Axis ARTPEC-8 SoC clock controller > > + > > +maintainers: > > +=C2=A0 - Jesper Nilsson > > + > > +description: | > > +=C2=A0 ARTPEC-8 clock controller is comprised of several CMU units, > > generating > > +=C2=A0 clocks for different domains. Those CMU units are modeled as > > separate device > > +=C2=A0 tree nodes, and might depend on each other. The root clock in > > that root tree > > +=C2=A0 is an external clock: OSCCLK (25 MHz). This external clock must > > be defined > > +=C2=A0 as a fixed-rate clock in dts. > > + > > +=C2=A0 CMU_CMU is a top-level CMU, where all base clocks are prepared > > using PLLs and > > +=C2=A0 dividers; all other clocks of function blocks (other CMUs) are > > usually > > +=C2=A0 derived from CMU_CMU. > > + > > +=C2=A0 Each clock is assigned an identifier and client nodes can use > > this identifier > > +=C2=A0 to specify the clock which they consume. All clocks available > > for usage > > +=C2=A0 in clock consumer nodes are defined as preprocessor macros in > > +=C2=A0 'include/dt-bindings/clock/axis,artpec8-clk.h' header. > > + > > +properties: > > +=C2=A0 compatible: > > +=C2=A0=C2=A0=C2=A0 enum: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-cmu > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-bus > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-core > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-cpucl > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-fsys > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-imem > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - axis,artpec8-cmu-peri > > + > > +=C2=A0 clocks: > > +=C2=A0=C2=A0=C2=A0 minItems: 1 > > +=C2=A0=C2=A0=C2=A0 maxItems: 5 > > + > > +=C2=A0 clock-names: > > +=C2=A0=C2=A0=C2=A0 minItems: 1 > > +=C2=A0=C2=A0=C2=A0 maxItems: 5 > > + > > +=C2=A0 "#clock-cells": > > +=C2=A0=C2=A0=C2=A0 const: 1 > > + > > +=C2=A0 reg: > > +=C2=A0=C2=A0=C2=A0 maxItems: 1 >=20 > reg goes second, after compatible (Samsung bindings are not the best > example because I converted them long time ago before many coding > style > practices were encouraged) Ok, I will move the reg property. >=20 > > + > > +required: > > +=C2=A0 - compatible > > +=C2=A0 - reg > > +=C2=A0 - "#clock-cells" > > +=C2=A0 - clocks > > +=C2=A0 - clock-names > > + > > +allOf: > > +=C2=A0 - if: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 contains: >=20 > Drop contains. Ok, I will remove the contains wherever applicable. >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 con= st: axis,artpec8-cmu-cmu > > + > > +=C2=A0=C2=A0=C2=A0 then: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clocks: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 items: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - d= escription: External reference clock (25 MHz) > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 items: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - c= onst: fin_pll > > + > > +=C2=A0 - if: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 compatible: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 contains: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 con= st: axis,artpec8-cmu-bus > > + > > +=C2=A0=C2=A0=C2=A0 then: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 properties: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clocks: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 items: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - d= escription: External reference clock (25 MHz) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - d= escription: CMU_BUS BUS clock (from CMU_CMU) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - d= escription: CMU_BUS DLP clock (from CMU_CMU) > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clock-names: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 items: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - c= onst: fin_pll > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - c= onst: dout_clkcmu_bus_bus > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - c= onst: dout_clkcmu_bus_dlp >=20 > All these names should be changed to match what is the input. Look at > latest bindings, we moved away from that style. Ok, I will modify clock-names to "bus" and "dlp" and will update at the other related places also. Thanks, Hakyeong Kim >=20 >=20 >=20 > Best regards, > Krzysztof