From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: Ryan.Wanner@microchip.com, mturquette@baylibre.com,
sboyd@kernel.org, alexandre.belloni@bootlin.com,
nicolas.ferre@microchip.com
Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, varshini.rajendran@microchip.com
Subject: Re: [PATCH v4 10/31] clk: at91: clk-generated: use clk_parent_data
Date: Mon, 20 Oct 2025 22:39:48 +0300 [thread overview]
Message-ID: <ff968ce4-9490-4e19-981b-7a5e9a842b68@tuxon.dev> (raw)
In-Reply-To: <645beaecf4b81c7e08f8adf3b9c74fa4b0176993.1758226719.git.Ryan.Wanner@microchip.com>
Hi, Ryan,
On 9/19/25 00:15, Ryan.Wanner@microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
>
> Use struct clk_parent_data instead of struct parent_hw as this leads
> to less usage of __clk_get_hw() in SoC specific clock drivers and simpler
> conversion of existing SoC specific clock drivers from parent_names to
> modern clk_parent_data structures.
>
> Remove the last of the usage of __clk_get_hw().
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> [ryan.wanner@microchip.com: Added SAMA7D65 and SAM9X75 SoCs to the
> clk-generated changes. Adjust clk name variable order.]
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> drivers/clk/at91/clk-generated.c | 8 +++----
> drivers/clk/at91/pmc.h | 2 +-
> drivers/clk/at91/sam9x7.c | 38 ++++++++++++++---------------
> drivers/clk/at91/sama7d65.c | 41 +++++++++++++++++---------------
> drivers/clk/at91/sama7g5.c | 39 ++++++++++++++++--------------
> 5 files changed, 67 insertions(+), 61 deletions(-)
>
[...]
> static void __init sama7d65_pmc_setup(struct device_node *np)
> {
> - const char *main_xtal_name;
> + const char *main_xtal_name, *md_slck_name, *td_slck_name;
> struct pmc_data *sama7d65_pmc;
> const char *parent_names[11];
> void **alloc_mem = NULL;
> int alloc_mem_size = 0;
> struct regmap *regmap;
> struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw;
> - struct clk_hw *td_slck_hw, *md_slck_hw;
> struct clk_parent_data parent_data[10];
> - struct clk_hw *parent_hws[10];
> bool bypass;
> int i, j;
>
> - td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck"));
> - md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck"));
> + i = of_property_match_string(np, "clock-names", "td_slck");
> + if (i < 0)
> + return;
> + td_slck_name = of_clk_get_parent_name(np, i);
> +
> + i = of_property_match_string(np, "clock-names", "md_slck");
> + if (i < 0)
> + return;
> + md_slck_name = of_clk_get_parent_name(np, i);
> +
> i = of_property_match_string(np, "clock-names", "main_xtal");
>
Please drop the resulting empty line here.
> - if (!td_slck_hw || !md_slck_hw || !i)
> + if (i < 0)
> return;
> main_xtal_name = of_clk_get_parent_name(np, i);
>
> @@ -1218,8 +1224,8 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
> sama7d65_pmc->chws[PMC_MCK] = hw;
> sama7d65_mckx[PCK_PARENT_HW_MCK0].hw = hw;
>
> - parent_data[0] = AT91_CLK_PD_NAME("md_slck");
> - parent_data[1] = AT91_CLK_PD_NAME("td_slck");
> + parent_data[0] = AT91_CLK_PD_NAME(md_slck_name);
> + parent_data[1] = AT91_CLK_PD_NAME(td_slck_name);
> parent_data[2] = AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]);
> for (i = PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7d65_mckx); i++) {
> u8 num_parents = 3 + sama7d65_mckx[i].ep_count;
> @@ -1264,8 +1270,8 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
> if (IS_ERR(hw))
> goto err_free;
>
> - parent_data[0] = AT91_CLK_PD_NAME("md_slck");
> - parent_data[1] = AT91_CLK_PD_NAME("td_slck");
> + parent_data[0] = AT91_CLK_PD_NAME(md_slck_name);
> + parent_data[1] = AT91_CLK_PD_NAME(td_slck_name);
> parent_data[2] = AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]);
> parent_data[3] = AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw);
> parent_data[4] = AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw);
> @@ -1315,13 +1321,12 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
> sama7d65_pmc->phws[sama7d65_periphck[i].id] = hw;
> }
>
> - parent_hws[0] = md_slck_hw;
> - parent_hws[1] = td_slck_hw;
> - parent_hws[2] = sama7d65_pmc->chws[PMC_MAIN];
> - parent_hws[3] = sama7d65_pmc->chws[PMC_MCK1];
> + parent_data[0] = AT91_CLK_PD_NAME(md_slck_name);
> + parent_data[1] = AT91_CLK_PD_NAME(td_slck_name);
> + parent_data[2] = AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]);
> + parent_data[3] = AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MCK1]);
> for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) {
> u8 num_parents = 4 + sama7d65_gck[i].pp_count;
> - struct clk_hw *tmp_parent_hws[8];
> u32 *mux_table;
>
> mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
> @@ -1338,15 +1343,13 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
> u8 pll_id = sama7d65_gck[i].pp[j].pll_id;
> u8 pll_compid = sama7d65_gck[i].pp[j].pll_compid;
>
> - tmp_parent_hws[j] = sama7d65_plls[pll_id][pll_compid].hw;
> + parent_data[4 + j] = AT91_CLK_PD_HW(sama7d65_plls[pll_id][pll_compid].hw);
> }
> - PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws,
> - sama7d65_gck[i].pp_count);
>
> hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
> &sama7d65_pcr_layout,
> sama7d65_gck[i].n, NULL,
> - parent_hws, mux_table,
> + parent_data, mux_table,
> num_parents,
> sama7d65_gck[i].id,
> &sama7d65_gck[i].r,
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index ddd5ad318990..ddbf69beb495 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -971,24 +971,30 @@ static const struct clk_pcr_layout sama7g5_pcr_layout = {
>
> static void __init sama7g5_pmc_setup(struct device_node *np)
> {
> - const char *main_xtal_name;
> + const char *main_xtal_name, *md_slck_name, *td_slck_name;
> struct pmc_data *sama7g5_pmc;
> void **alloc_mem = NULL;
> int alloc_mem_size = 0;
> struct regmap *regmap;
> struct clk_hw *hw, *main_rc_hw, *main_osc_hw;
> - struct clk_hw *td_slck_hw, *md_slck_hw;
> struct clk_parent_data parent_data[10];
> - struct clk_hw *parent_hws[10];
> struct clk *main_xtal;
> bool bypass;
> int i, j;
>
> - td_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "td_slck"));
> - md_slck_hw = __clk_get_hw(of_clk_get_by_name(np, "md_slck"));
> + i = of_property_match_string(np, "clock-names", "td_slck");
> + if (i < 0)
> + return;
> + td_slck_name = of_clk_get_parent_name(np, i);
> +
> + i = of_property_match_string(np, "clock-names", "md_slck");
> + if (i < 0)
> + return;
> + md_slck_name = of_clk_get_parent_name(np, i);
> +
> i = of_property_match_string(np, "clock-names", "main_xtal");
>
Please drop the resulting empty line here.
next prev parent reply other threads:[~2025-10-20 19:39 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 21:15 [PATCH v4 00/31] clk: at91: add support for parent_data and Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 01/31] clk: at91: pmc: add macros for clk_parent_data Ryan.Wanner
2025-10-20 19:40 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 02/31] clk: at91: pmc: Move macro to header file Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 03/31] clk: at91: sam9x75: switch to parent_hw and parent_data Ryan.Wanner
2025-10-20 19:38 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 04/31] clk: at91: clk-sam9x60-pll: use clk_parent_data Ryan.Wanner
2025-10-20 19:41 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 05/31] clk: at91: clk-peripheral: switch to clk_parent_data Ryan.Wanner
2025-10-20 19:41 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 06/31] clk: at91: clk-main: switch to clk parent data Ryan.Wanner
2025-10-20 19:42 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 07/31] clk: at91: clk-utmi: use clk_parent_data Ryan.Wanner
2025-10-20 19:43 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 08/31] clk: at91: clk-master: " Ryan.Wanner
2025-10-20 19:44 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 09/31] clk: at91: clk-programmable: " Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 10/31] clk: at91: clk-generated: " Ryan.Wanner
2025-10-20 19:39 ` Claudiu Beznea [this message]
2025-10-20 19:45 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 11/31] clk: at91: clk-usb: add support for clk_parent_data Ryan.Wanner
2025-10-20 19:17 ` Claudiu Beznea
2025-12-18 16:23 ` Ryan.Wanner
2025-12-23 14:00 ` claudiu beznea
2026-01-05 17:58 ` Ryan.Wanner
2026-01-10 15:03 ` Claudiu Beznea
2026-01-12 21:25 ` Ryan Wanner
2026-01-16 6:57 ` claudiu beznea
2025-09-18 21:15 ` [PATCH v4 12/31] clk: at91: clk-system: use clk_parent_data Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 13/31] clk: at91: sama7d65: switch to parent_hw and parent_data Ryan.Wanner
2025-10-20 19:14 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 14/31] clk: at91: clk-pll: add support for parent_hw Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 15/31] clk: at91: clk-audio-pll: " Ryan.Wanner
2025-09-18 21:15 ` [PATCH v4 16/31] clk: at91: clk-plldiv: " Ryan.Wanner
2025-10-20 19:12 ` Claudiu Beznea
2025-09-18 21:15 ` [PATCH v4 17/31] clk: at91: clk-h32mx: " Ryan.Wanner
2025-10-20 19:12 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 18/31] clk: at91: clk-i2s-mux: " Ryan.Wanner
2025-10-20 19:13 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 19/31] clk: at91: clk-smd: add support for clk_parent_data Ryan.Wanner
2025-10-20 19:14 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 20/31] clk: at91: clk-slow: add support for parent_hw Ryan.Wanner
2025-10-20 19:17 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 21/31] clk: at91: dt-compat: switch to parent_hw and parent_data Ryan.Wanner
2025-10-20 19:15 ` Claudiu Beznea
2026-01-09 17:03 ` Ryan Wanner
2026-01-10 15:07 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 22/31] clk: at91: sam9x60: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 23/31] clk: at91: sama5d2: " Ryan.Wanner
2025-10-20 19:19 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 24/31] clk: at91: sama5d3: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 25/31] clk: at91: sama5d4: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 26/31] clk: at91: at91sam9x5: " Ryan.Wanner
2025-10-20 19:19 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 27/31] clk: at91: at91rm9200: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 28/31] clk: at91: at91sam9260: " Ryan.Wanner
2025-10-20 19:35 ` Claudiu Beznea
2025-09-18 21:16 ` [PATCH v4 29/31] clk: at91: at91sam9g45: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 30/31] clk: at91: at91sam9n12: " Ryan.Wanner
2025-09-18 21:16 ` [PATCH v4 31/31] clk: at91: at91sam9rl: switch to clk_parent_data Ryan.Wanner
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