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[86.58.12.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4ba0236f03esm56975655e9.3.2026.11.10.07.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 07:57:14 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Stephen Boyd , Brian Masney , Jerome Brunet , Chen-Yu Tsai , Samuel Holland , Maxime Ripard , Andre Przywara , aiyengar1990@gmail.com Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] clk: sunxi-ng: h616: Fix the EMAC 25 MHz clock parent and divider Date: Tue, 10 Nov 2026 16:57:13 +0100 Message-ID: In-Reply-To: <20261110-h616-clk-emac-spdif-v1-1-e5e36e8963e4@gmail.com> References: <20261110-h616-clk-emac-spdif-v1-0-e5e36e8963e4@gmail.com> <20261110-h616-clk-emac-spdif-v1-1-e5e36e8963e4@gmail.com> X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne torek, 10. november 2026 ob 07:03:00 Srednjeevropski standardni =C4=8Da= s je Arun Iyengar via B4 Relay napisal(a): > From: Arun Iyengar >=20 > The H616 user manual (v1.0, 3.3.5.86 EPHY_25M_CLK_REG, 0x0970) gives the > EPHY 25 MHz clock as PLL_PERI0(1X) / 24, with bit 31 gating the output > and bit 30 gating the PLL_PERI0 input. The driver models it as a plain > gate below ahb3, so the clock framework reports the AHB3 rate (200 MHz) > for a clock that runs at 25 MHz, and the clock tree does not show that > the PHY clock depends on pll-periph0 rather than on the AHB3 bus. >=20 > Model it like the D1 driver does: a gate with a fixed /24 pre-divider > below pll-periph0. The register writes do not change, only the parent > and the reported rate do. On an Orange Pi Zero2, emac-25m now reads > 25000000 with pll-periph0 (600 MHz) as its parent. >=20 > Fixes: 88dde5e23da1 ("clk: sunxi-ng: Add support for the Allwinner H616 C= CU") > Signed-off-by: Arun Iyengar Acked-by: Jernej Skrabec Best regards, Jernej > --- > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-n= g/ccu-sun50i-h616.c > index 955c614830fa..d2625fec651a 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > @@ -489,8 +489,17 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", = nand_spi_parents, 0x944, > static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0= ); > static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0= ); > =20 > -static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970, > - BIT(31) | BIT(30), 0); > +/* > + * The EPHY 25 MHz clock is PLL_PERI0(1X) / 24, gated by both the special > + * clock gate (bit 31) and the PLL_PERI0 input gate (bit 30). > + */ > +static const struct clk_hw *emac_25m_parents[] =3D { > + &pll_periph0_clk.common.hw > +}; > + > +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac_25m_clk, "emac-25m", > + emac_25m_parents, 0x970, > + BIT(31) | BIT(30), 24, 0); > =20 > static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0),= 0); > static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1),= 0); >=20 >=20