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Wed, 02 Sep 2026 03:29:23 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: Krzysztof Kozlowski , Lee Jones , Linus Walleij Cc: Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King , Brian Masney , Jerome Brunet , Manivannan Sadhasivam , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, mfd@lists.linux.dev Subject: Re: [PATCH v11 04/12] ARM: dts: zte: Declare zx297520v3 CRM device nodes Date: Wed, 02 Sep 2026 13:29:12 +0300 Message-ID: In-Reply-To: <20260826-zx29clk-v11-4-f8ad59c6426c@gmail.com> References: <20260826-zx29clk-v11-0-f8ad59c6426c@gmail.com> <20260826-zx29clk-v11-4-f8ad59c6426c@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPartatLajs3yRkirKyBuoKqPXQ"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPartatLajs3yRkirKyBuoKqPXQ Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Date: Wed, 02 Sep 2026 13:29:12 +0300 Message-ID: In-Reply-To: <20260826-zx29clk-v11-4-f8ad59c6426c@gmail.com> MIME-Version: 1.0 Hi List, and in particular Krzysztof, Am Mittwoch, 26. August 2026, 00:24:03 Ostafrikanische Zeit schrieb Stefan= =20 D=C3=B6singer: > This patch adds DT nodes for the main clock and reset controllers on the > zx297520v3 board. It replaces the temporary placeholder UART clocks with > the proper clocks exported by topcrm and lspcrm. >=20 > Signed-off-by: Stefan D=C3=B6singer >=20 This patch is the only one of my Z29 Clock and Reset series that has not se= en=20 review comments Did it slip through the cracks? Linus Walleij added his R-B on the patch that added the mostly stub DSTI fi= le,=20 so I added him to the mail too. Cheers, Stefan > --- >=20 > Version 11: Improved the above the line commit description, removing > references to "previous patches" that won't make sense when reading it > in the kernel commit log. >=20 > Version 10: Fix issues with dt-check-style --mode=3Dstrict in newly added > code, but left issues in existing nodes alone. >=20 > Version 9: > Sort new nodes by mmio address > rename syscon-reboot to "reboot" > adjust to changes in bindings >=20 > Version 7: > Add phy nodes to topcrm > Remove syscon from matrixclk again > Adapt remove now-removed extra clk inputs from matrix > Add reset to LSP > osc26m -> clock-26m for the fixed rate clocks, likewise for 32k >=20 > Version 6: > Add syscon to matrixclk >=20 > Version 5: > Re-name from *clk to *crm > Add the syscon-reboot node here because the binding requires it > Re-add accidentally dropped uart2 IRQ > --- > arch/arm/boot/dts/zte/zx297520v3.dtsi | 101 > ++++++++++++++++++++++++++++++---- 1 file changed, 89 insertions(+), 12 > deletions(-) >=20 > diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi > b/arch/arm/boot/dts/zte/zx297520v3.dtsi index a16c30a164bb..ebac3cd137df > 100644 > --- a/arch/arm/boot/dts/zte/zx297520v3.dtsi > +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi > @@ -3,12 +3,26 @@ > * Copyright (c) 2026 Stefan D=C3=B6singer > */ >=20 > +#include > #include > +#include >=20 > / { > #address-cells =3D <1>; > #size-cells =3D <1>; >=20 > + osc26m: clock-26m { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <26000000>; > + }; > + > + osc32k: clock-32k { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <32768>; > + }; > + > cpus { > #address-cells =3D <1>; > #size-cells =3D <0>; > @@ -20,15 +34,6 @@ cpu@0 { > }; > }; >=20 > - /* Base bus clock and default for the UART. It will be replaced once=20 a > clock driver has - * been added. > - */ > - uartclk: uartclk-26000000 { > - #clock-cells =3D <0>; > - compatible =3D "fixed-clock"; > - clock-frequency =3D <26000000>; > - }; > - > timer { > compatible =3D "arm,armv7-timer"; > interrupts =3D , > @@ -75,18 +80,87 @@ uart0: serial@131000 { > arm,primecell-periphid =3D <0x0018c011>; > reg =3D <0x00131000 0x1000>; > interrupts =3D ; > - clocks =3D <&uartclk>, <&uartclk>; > + clocks =3D <&topcrm ZX297520V3_UART0_WCLK>, > + <&topcrm ZX297520V3_UART0_PCLK>; > clock-names =3D "uartclk", "apb_pclk"; > + resets =3D <&topcrm ZX297520V3_UART0_RESET>; > + > status =3D "disabled"; > }; >=20 > + topcrm: clock-controller@13b000 { > + compatible =3D "zte,zx297520v3-topcrm", "syscon"; > + reg =3D <0x0013b000 0x400>; > + #clock-cells =3D <1>; > + clocks =3D <&osc26m>, <&osc32k>; > + clock-names =3D "osc26m", "osc32k"; > + interrupts =3D , > + , > + , > + ; > + interrupt-names =3D "usb-up", "usb-down", > + "hsic-up", "hsic-down"; > + #phy-cells =3D <1>; > + #reset-cells =3D <1>; > + > + reboot { > + compatible =3D "syscon-reboot"; > + mask =3D <0x1>; > + offset =3D <0x0>; > + value =3D <0x1>; > + }; > + }; > + > + matrixcrm: clock-controller@1306000 { > + compatible =3D "zte,zx297520v3-matrixcrm"; > + reg =3D <0x01306000 0x400>; > + #clock-cells =3D <1>; > + clocks =3D <&osc26m>, <&osc32k>, > + <&topcrm ZX297520V3_AHB_PCLK>, > + <&topcrm ZX297520V3_MPLL>, > + <&topcrm ZX297520V3_MPLL_D5>, > + <&topcrm ZX297520V3_DPLL>, > + <&topcrm ZX297520V3_GPLL>, > + <&topcrm ZX297520V3_GPLL_D2>, > + <&topcrm ZX297520V3_GATED_OSC26M>; > + clock-names =3D "osc26m", "osc32k", "ahb", "mpll", > + "mpll-d5", "dpll", "gpll",=20 "gpll-d2", > + "wclk-osc26m"; > + #hwlock-cells =3D <1>; > + #reset-cells =3D <1>; > + }; > + > + lspcrm: clock-controller@1400000 { > + compatible =3D "zte,zx297520v3-lspcrm"; > + reg =3D <0x01400000 0x100>; > + #clock-cells =3D <1>; > + clocks =3D <&matrixcrm=20 ZX297520V3_LSP_MPLL_D5_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_MPLL_D4_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_MPLL_D6_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_MPLL_D8_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_MPLL_D12_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_OSC26M_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_OSC32K_WCLK>, > + <&matrixcrm ZX297520V3_LSP_PCLK>, > + <&matrixcrm ZX297520V3_LSP_TDM_WCLK>, > + <&matrixcrm=20 ZX297520V3_LSP_DPLL_D4_WCLK>; > + clock-names =3D "mpll-d5", "mpll-d4", "mpll-d6", > + "mpll-d8", "mpll-d12", "osc26m",=20 "osc32k", > + "pclk", "tdm-wclk", "dpll-d4"; > + #reset-cells =3D <1>; > + resets =3D <&matrixcrm ZX297520V3_LSP_RESET>; > + }; > + > uart1: serial@1408000 { > compatible =3D "arm,pl011", "arm,primecell"; > arm,primecell-periphid =3D <0x0018c011>; > reg =3D <0x01408000 0x1000>; > interrupts =3D ; > - clocks =3D <&uartclk>, <&uartclk>; > + clocks =3D <&lspcrm ZX297520V3_UART1_WCLK>, > + <&lspcrm ZX297520V3_UART1_PCLK>; > clock-names =3D "uartclk", "apb_pclk"; > + resets =3D <&lspcrm ZX297520V3_UART1_RESET>; > + > status =3D "disabled"; > }; >=20 > @@ -95,8 +169,11 @@ uart2: serial@140d000 { > arm,primecell-periphid =3D <0x0018c011>; > reg =3D <0x0140d000 0x1000>; > interrupts =3D ; > - clocks =3D <&uartclk>, <&uartclk>; > + clocks =3D <&lspcrm ZX297520V3_UART2_WCLK>, > + <&lspcrm ZX297520V3_UART2_PCLK>; > clock-names =3D "uartclk", "apb_pclk"; > + resets =3D <&lspcrm ZX297520V3_UART2_RESET>; > + > status =3D "disabled"; > }; > }; >=20 > -- > 2.54.0 --nextPartatLajs3yRkirKyBuoKqPXQ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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