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Thu, 01 Oct 2026 00:39:45 -0700 (PDT) Received: from dev-ag ([102.33.165.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2e31dc70adsm100397966b.68.2026.10.01.00.39.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 00:39:44 -0700 (PDT) From: Andrew Gaylard To: Brian Masney Cc: linux-clk@vger.kernel.org, qinjian@cqplus1.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] clk: sp7021: fix infrastructure clocks clobbering PLL provider entries In-Reply-To: <179069997903.213266.2923932929883625249.b4-reply@b4> (Brian Masney's message of "Tue, 29 Sep 2026 12:39:39 -0400") References: <20260820130224.1584902-1-ag@ffroot.co.za> <179069997903.213266.2923932929883625249.b4-reply@b4> User-Agent: mu4e 1.12.14; emacs 30.2 Date: Thu, 01 Oct 2026 09:39:40 +0200 Message-ID: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Brian Masney writes: > Hi Andrew, > > On 2026-08-20 15:02 +0200, Andrew Gaylard wrote: >> The sp_clk_gates[] array previously included 9 infrastructure gate >> clocks (CLK_SYSTEM, CLK_IOCTL, etc.) appended after the 64 DT-visible >> gate clocks. The registration loop used the array index directly as the >> hws[] index, so infrastructure clocks at positions 64-72 overwrote >> hws[PLL_A] through hws[PLL_SYS]. [...] > > This patch does not apply against the tree. > > Brian Hi Brian, Thanks for looking at this path. I have a better fix now, but it needs another series [0] to land first. [0] https://lore.kernel.org/linux-arm-kernel/20260924164922.117236-1-ag@ffroot.co.za/ -- Andrew