From: sashiko-bot@kernel.org
To: "Changhuang Liang" <changhuang.liang@starfivetech.com>
Cc: linux-clk@vger.kernel.org
Subject: Re: [PATCH v1 6/6] reset: starfive: Add StarFive JHB100 System-0 reset driver
Date: Tue, 13 Oct 2026 10:46:27 +0000 [thread overview]
Message-ID: <sashiko-outbox-169543@kernel.org> (raw)
In-Reply-To: <20261013102707.9207-7-changhuang.liang@starfivetech.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] build: missing dt-bindings header starfive,jhb100-crg.h
--
commit b52257e208a93d7e9c3c20b66b5cf444b957168b
Author: Changhuang Liang <changhuang.liang@starfivetech.com>
reset: starfive: Add StarFive JHB100 System-0 reset driver
Add the auxiliary reset driver for the StarFive JHB100 SoC. It binds to
the auxiliary devices registered by the JHB100 clock generator drivers
and uses the register base handed over as platform data.
> diff --git a/drivers/reset/starfive/reset-starfive-jhb100.c b/drivers/reset/starfive/reset-starfive-jhb100.c
> new file mode 100644
> index 0000000000000..129e5e8af251c
> --- /dev/null
> +++ b/drivers/reset/starfive/reset-starfive-jhb100.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Reset driver for the StarFive JHB100 SoC
> + *
> + * Copyright (C) 2024 StarFive Technology Co., Ltd.
> + *
> + * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> + */
> +
> +#include <dt-bindings/reset/starfive,jhb100-crg.h>
[Severity: Low]
Is this include missing from the current tree? Building the reset driver
with CONFIG_RESET_STARFIVE_JHB100 enabled fails because the dt-bindings
header starfive,jhb100-crg.h does not exist in this revision.
> +#include <linux/auxiliary_bus.h>
> +#include <soc/starfive/reset-starfive-jh71x0.h>
> +
> +#include "reset-starfive-jh71x0.h"
> +
> +static const struct jh71x0_reset_map jhb100_sys0_map[] = {
> + { JHB100_SYS0RST_RESOURCE_ARB, 0 },
This array relies on the missing header for macros like
JHB100_SYS0RST_RESOURCE_ARB, which results in undefined identifier errors
during compilation.
Do the device tree bindings need to be introduced in an earlier patch or
combined with this one to ensure git bisect does not break due to the build
failure?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261013102707.9207-1-changhuang.liang@starfivetech.com?part=6
next prev parent reply other threads:[~2026-10-13 10:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 10:27 [PATCH v1 0/6] Add System-0 CRG for JHB100 SoC Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 2/6] clk: starfive: jh71x0: Move reset controller registration to jh71x0 common code Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 3/6] clk: starfive: jh71x0: Add generic CRG probe helper Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 5/6] reset: starfive: jh71x0: Support discontiguous reset IDs Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 6/6] reset: starfive: Add StarFive JHB100 System-0 reset driver Changhuang Liang
2026-10-13 10:46 ` sashiko-bot [this message]
[not found] ` <20261013102707.9207-5-changhuang.liang@starfivetech.com>
2026-10-13 10:42 ` [PATCH v1 4/6] clk: starfive: Add JHB100 System-0 clock generator driver sashiko-bot
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