Re: [PATCH DNM RFC 15/16] arm64: dts: qcom: sm8650: Drop required-opps

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: pcie: power domain starvation for Gen3/Gen4
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commit 467d81619c5b5922cc360aaaf647dd4b6a900f09
Author: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

arm64: dts: qcom: sm8650: Drop required-opps

This commit drops the required-opps properties from various OPP tables in
the SM8650 device tree. It assumes that clock controllers now take care of
their power requirements.

> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 0847cfb35954e..47d7be98128e2 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
[ ... ]
> @@ -3749,7 +3745,6 @@ opp-10000000-2 {
>  				/* 8 GT/s x1 */
>  				opp-8000000-3 {
>  					opp-hz = /bits/ 64 <8000000>;
> -					required-opps = <&rpmhpd_opp_nom>;

[Severity: High]
Does dropping this required-opps break the static PM domain vote for PCIe
Gen3 and Gen4?

The qcom,pcie driver uses pseudo-frequencies (like 8000000 for Gen3) in the
OPP table to represent link speeds rather than actual clock frequencies. When
the OPP framework processes this, it attempts to set the rate of the first
clock listed for the device (GCC_PCIE_0_AUX_CLK or GCC_PCIE_1_AUX_CLK).

However, in drivers/clk/qcom/gcc-sm8650.c, gcc_pcie_0_aux_clk_src_dvfs is
fixed at 19.2MHz and only maps to LOW_SVS:

drivers/clk/qcom/gcc-sm8650.c:
static const struct qcom_clk_dvfs_data gcc_pcie_0_aux_clk_src_dvfs = {
	.pd_indices = (const unsigned int[]) { DT_PMDOMAIN_CX, DT_PMDOMAIN_MX },
	.num_pd_indices = 2,
	.rates = (const struct qcom_clk_dvfs_rate[]) {
		{ 19200000, RPMH_REGULATOR_LEVEL_LOW_SVS },
	},
	.num_rates = 1,
};

Without the direct power domain vote, the PCIe controller will run at LOW_SVS
voltage instead of the NOM voltage required by Gen3 and higher. Could this
lead to power domain starvation, causing link training failures or bus hangs
when accessing an under-powered PHY on boards booting with a PCIe Gen3 or
Gen4 device?

>  					opp-peak-kBps = <984500 1>;
>  					opp-level = <3>;
>  				};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261014-topic-qc_clk_dvfs-v1-0-3041b788e9f7@oss.qualcomm.com?part=15