From: sashiko-bot@kernel.org
To: "James Hilliard" <james.hilliard1@gmail.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-sunxi@lists.linux.dev, robh@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH v12 1/5] dt-bindings: pwm: allwinner: add h616 pwm compatible
Date: Wed, 04 Nov 2026 19:32:04 +0000 [thread overview]
Message-ID: <sashiko-outbox-197954@kernel.org> (raw)
In-Reply-To: <20261104-h616-pwm-v8-v12-1-8ed39b0dba69@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: pwm: allwinner: split sun50i-h616-pwm into separate schema
--
commit e6edbdd3d4cc396aa4ef672101ddfbb0d8e92bc7
Author: Richard Genoud <richard.genoud@bootlin.com>
dt-bindings: pwm: allwinner: add h616 pwm compatible
This commit extends the Allwinner sun4i-a10-pwm binding schema to document
the Allwinner H616 PWM controller compatible (allwinner,sun50i-h616-pwm)
and its #clock-cells property for exporting channel bypass clocks.
> diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> index 1197858e431f2..3b1819c8630cc 100644
> --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
> @@ -14,6 +14,13 @@ properties:
> "#pwm-cells":
> const: 3
>
> + "#clock-cells":
> + const: 1
> + description:
> + The cell selects the PWM channel whose hardware bypass path is exported
> + as a clock. Its rate follows the selected shared pair source and divider;
> + the PWM period, duty-cycle and polarity logic is bypassed.
> +
> compatible:
> oneOf:
> - const: allwinner,sun4i-a10-pwm
> @@ -36,6 +43,7 @@ properties:
> - const: allwinner,sun50i-h5-pwm
> - const: allwinner,sun5i-a13-pwm
> - const: allwinner,sun50i-h6-pwm
> + - const: allwinner,sun50i-h616-pwm
>
> reg:
> maxItems: 1
> @@ -62,7 +70,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: allwinner,sun50i-h6-pwm
> + enum:
> + - allwinner,sun50i-h6-pwm
> + - allwinner,sun50i-h616-pwm
>
> then:
> properties:
> @@ -83,6 +93,27 @@ allOf:
> clocks:
> maxItems: 1
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: allwinner,sun50i-h616-pwm
> +
> + then:
> + properties:
> + clocks:
> + minItems: 2
> +
> + clock-names:
> + minItems: 2
> +
> + required:
> + - "#clock-cells"
> +
> + else:
> + properties:
> + "#clock-cells": false
[Severity: Low]
As reported by Sashiko on v11 [1], this isn't a bug, but since the H616 PWM
controller is a distinct hardware block that also acts as a clock provider via
#clock-cells, extending Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
requires defining #clock-cells under top-level properties only to disallow it in
an else branch for all ten older compatibles, while splitting the H616 clocks
and clock-names constraints across two separate if-then-else blocks in allOf.
Would it be cleaner to split allwinner,sun50i-h616-pwm into its own binding
schema document instead of adding another conditional block here?
[1] https://lore.kernel.org/r/20261103-h616-pwm-v8-v11-1-07abb59575c3@gmail.com
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261104-h616-pwm-v8-v12-0-8ed39b0dba69@gmail.com?part=1
next prev parent reply other threads:[~2026-11-04 19:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 19:24 [PATCH v12 0/5] Introduce Allwinner H616 PWM controller James Hilliard
2026-11-04 19:24 ` [PATCH v12 1/5] dt-bindings: pwm: allwinner: add h616 pwm compatible James Hilliard
2026-11-04 19:32 ` sashiko-bot [this message]
2026-11-04 19:24 ` [PATCH v12 2/5] pwm: sun8i: Add H616 PWM support James Hilliard
2026-11-04 19:24 ` [PATCH v12 3/5] pwm: sun8i: export the bypass outputs as clocks James Hilliard
2026-11-04 19:24 ` [PATCH v12 4/5] arm64: dts: allwinner: h616: add PWM controller James Hilliard
2026-11-04 19:24 ` [PATCH v12 5/5] MAINTAINERS: Add entry on Allwinner sun8i/H616 PWM driver James Hilliard
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