Linux clock framework development
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From: sashiko-bot@kernel.org
To: "Gabriel Fernandez" <gabriel.fernandez@foss.st.com>
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 5/8] clk: stm32mp25: add clock for D3 peripherals allocation for Cortex-CM0
Date: Fri, 06 Nov 2026 15:56:37 +0000	[thread overview]
Message-ID: <sashiko-outbox-201746@kernel.org> (raw)
In-Reply-To: <20261106-ups_mp25_clk_update-v3-5-4a32f68119ed@foss.st.com>

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] clk: stm32mp25: mismatch between commit log and MSI_KER_ON
  parent assignment
--

commit aad9d612e6cd2adba430e970b7e94c3f5b129bc6
Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

clk: stm32mp25: add clock for D3 peripherals allocation for Cortex-CM0

This commit adds autonomous mode (GATE_<IP>AM) and CPU3 allocation
(GATE_<IP>C3) clock gates for D3 peripherals on STM32MP25, along with new
RCC input clock indices and the C3 reset.

> diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c
> index fa025a9f3f378..e3a2e5ea775c8 100644
> --- a/drivers/clk/stm32/clk-stm32mp25.c
> +++ b/drivers/clk/stm32/clk-stm32mp25.c
[ ... ]
> @@ -518,6 +564,77 @@ static struct clk_stm32_gate ck_ker_adf1 = {
>  	.hw.init = CLK_HW_INIT_INDEX("ck_ker_adf1", FLEXGEN_42, &clk_stm32_gate_ops, 0),
>  };
>  
> +static struct clk_stm32_gate ck_ker_adf1_am = {
> +	.gate_id = GATE_ADF1AM,
> +	.hw.init = CLK_HW_INIT_HW("ck_ker_adf1_am", &ck_ker_adf1.hw, &clk_stm32_gate_ops, 0),
> +};
> +
> +/* C3 */
> +static struct clk_stm32_gate ck_cpu3 = {
> +	.gate_id = GATE_C3,
> +	.hw.init = CLK_HW_INIT_INDEX("ck_cpu3", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
> +};
> +
> +static struct clk_stm32_gate ck_cpu3_am = {
> +	.gate_id = GATE_C3AM,
> +	.hw.init = CLK_HW_INIT_HW("ck_cpu3_am", &ck_cpu3.hw, &clk_stm32_gate_ops, 0),
> +};
> +
> +static struct clk_stm32_gate ck_c3_adf1 = {
> +	.gate_id = GATE_ADF1C3,
> +	.hw.init = CLK_HW_INIT_INDEX("ck_c3_adf1", MSI_KER_ON, &clk_stm32_gate_ops, 0),
> +};

[Severity: Low]
Does the MSI_KER_ON parenting here match the commit message?

The commit message states that all the autonomous clocks (GATE_<IP>AM) have
the MSI KER clock as their parent so that MSIKERON is set for Stop modes.
In the code, however, the autonomous clocks (such as ck_ker_adf1_am and the
other ck_ker_*_am / ck_cpu3_am clocks) are parented to their respective
peripheral kernel clocks, while the CPU3 allocation clocks (ck_c3_*) are
the ones parented to MSI_KER_ON.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261106-ups_mp25_clk_update-v3-0-4a32f68119ed@foss.st.com?part=5

  reply	other threads:[~2026-11-06 15:56 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-06 15:35 [PATCH v3 0/8] clk: stm32mp25: add Cortex-M0 D3 clocks, ETR/STM and USB2PHY1 STP Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 1/8] clk: stm32mp25: define the number of clocks in the driver Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 2/8] dt-bindings: stm32: add kernel clocks for ETR and STM Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 3/8] clk: stm32mp25: update register with reference manual Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 4/8] dt-bindings: stm32: add clocks for Cortex-CM0 on stm32mp25 Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 5/8] clk: stm32mp25: add clock for D3 peripherals allocation for Cortex-CM0 Gabriel Fernandez
2026-11-06 15:56   ` sashiko-bot [this message]
2026-11-06 15:35 ` [PATCH v3 6/8] dt-bindings: stm32: add usb2phy1stp clock on stm32mp25 Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 7/8] clk: stm32mp25: add ck_ker_usb2phy1_stp clock Gabriel Fernandez
2026-11-06 15:35 ` [PATCH v3 8/8] dt-bindings: stm32: use reference manual names for ETR and STM bus clocks Gabriel Fernandez

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