Re: [PATCH v2 3/3] arm64: dts: qcom: ipq5210: Add NSS clock controller node

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] arm64: dts: qcom: ipq5210: xo_board uses xo_clk instead of
  ref_48mhz_clk
--

commit f6342940567706c16d7408b991562c108f13f6b3
Author: Luo Jie <jie.luo@oss.qualcomm.com>

arm64: dts: qcom: ipq5210: Add NSS clock controller node

This commit adds the NSS clock controller (nsscc) device tree node to
ipq5210.dtsi to provide clocks and resets for the networking blocks.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> index 0c1ede0f73b21..11915f8eb1567 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi
> @@ -331,6 +331,46 @@ frame@b128000 {
>  				status = "disabled";
>  			};
>  		};
> +
> +		nsscc: clock-controller@39b00000 {
> +			compatible = "qcom,ipq5210-nsscc";
> +			reg = <0x0 0x39b00000 0x0 0x100000>;
> +			/*
> +			 * Note: CMN PLL output clock names below are reversed relative
> +			 * to the hardware block they feed - IPQ5210_PPE_CLK is wired to
> +			 * the NSS hardware block ("nss") and IPQ5210_NSS_CLK is wired
> +			 * to the PPE hardware block ("ppe").
> +			 */
> +			clocks = <&xo_board>,
> +				 <&cmn_pll IPQ5210_PPE_CLK>,

[Severity: Medium]
Should xo_board be parented to <&ref_48mhz_clk> instead of <&xo_clk>?

arch/arm64/boot/dts/qcom/ipq5210.dtsi:
		ref_48mhz_clk: ref-48mhz-clk {
			compatible = "fixed-factor-clock";
			clocks = <&xo_clk>;
			#clock-cells = <0>;
		};
    ...
		xo_board: xo-board-clk {
			compatible = "fixed-factor-clock";
			clocks = <&xo_clk>;
			#clock-cells = <0>;
		};

arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts notes that xo_clk can be
48 MHz, 96 MHz, or 192 MHz, which the WiFi block divides down to the
48 MHz ref_48mhz_clk, and that xo_board is a fixed 24 MHz clock routed
from that 48 MHz WiFi output clock divided by 2.  Because xo_board uses
<&xo_clk> as its parent instead of <&ref_48mhz_clk> (unlike
ipq5424.dtsi, ipq5332.dtsi, and ipq9574.dtsi), on boards with a 96 MHz
or 192 MHz xo_clk, xo_board will resolve to 48 MHz or 96 MHz instead of
24 MHz, supplying the wrong XO reference rate to nsscc, gcc, and sdhc.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111-qcom_ipq5210_nsscc-v2-0-7e2c1dda3ed2@oss.qualcomm.com?part=3