From: Brijesh Singh <brijesh.singh@amd.com>
To: "Kirill A. Shutemov" <kirill@shutemov.name>
Cc: brijesh.singh@amd.com, Borislav Petkov <bp@alien8.de>,
x86@kernel.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, linux-efi@vger.kernel.org,
platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev,
linux-mm@kvack.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Joerg Roedel <jroedel@suse.de>,
Tom Lendacky <thomas.lendacky@amd.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Ard Biesheuvel <ardb@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Jim Mattson <jmattson@google.com>,
Andy Lutomirski <luto@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Sergio Lopez <slp@redhat.com>, Peter Gonda <pgonda@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
David Rientjes <rientjes@google.com>,
Dov Murik <dovmurik@linux.ibm.com>,
Tobin Feldman-Fitzthum <tobin@ibm.com>,
Michael Roth <michael.roth@amd.com>,
Vlastimil Babka <vbabka@suse.cz>, Andi Kleen <ak@linux.intel.com>,
"Dr . David Alan Gilbert" <dgilbert@redhat.com>,
brijesh.ksingh@gmail.com, tony.luck@intel.com,
marcorr@google.com, sathyanarayanan.kuppuswamy@linux.intel.com
Subject: Re: [PATCH v10 21/45] x86/mm: Add support to validate memory when changing C-bit
Date: Mon, 21 Feb 2022 13:54:03 -0600 [thread overview]
Message-ID: <1e27feca-9f48-5a14-be5c-abc12d2651b8@amd.com> (raw)
In-Reply-To: <20220221174121.ceeplpoaz63q72kv@box>
On 2/21/22 11:41, Kirill A. Shutemov wrote:
> On Wed, Feb 16, 2022 at 10:04:57AM -0600, Brijesh Singh wrote:
>> @@ -287,6 +301,7 @@ struct x86_platform_ops {
>> struct x86_legacy_features legacy;
>> void (*set_legacy_features)(void);
>> struct x86_hyper_runtime hyper;
>> + struct x86_guest guest;
>> };
>
> I used 'cc' instead of 'guest'. 'guest' looks too generic.
I am fine with either of them.
>
> Also, I'm not sure why not to use pointer to ops struct instead of stroing
> them directly in x86_platform. Yes, it is consistent with 'hyper', but I
> don't see it as a strong argument.
>
>>
>> index b4072115c8ef..a55477a6e578 100644
>> --- a/arch/x86/mm/pat/set_memory.c
>> +++ b/arch/x86/mm/pat/set_memory.c
>> @@ -2012,8 +2012,15 @@ static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc)
>> */
>> cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));
>>
>> + /* Notify HV that we are about to set/clr encryption attribute. */
>> + x86_platform.guest.enc_status_change_prepare(addr, numpages, enc);
>> +
>> ret = __change_page_attr_set_clr(&cpa, 1);
>
> This doesn't cover difference in flushing requirements. Can we get it too?
>
Yes, we can work to include that too.
>>
>> + /* Notify HV that we have succesfully set/clr encryption attribute. */
>> + if (!ret)
>> + x86_platform.guest.enc_status_change_finish(addr, numpages, enc);
>> +
>
> Any particular reason you moved it above cpa_flush()? I don't think it
> makes a difference for TDX, but still.
>
It does not make any difference for the SNP as well. We can keep it
where it was.
>> /*
>> * After changing the encryption attribute, we need to flush TLBs again
>> * in case any speculative TLB caching occurred (but no need to flush
>> @@ -2023,12 +2030,6 @@ static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc)
>> */
>> cpa_flush(&cpa, 0);
>>
>> - /*
>> - * Notify hypervisor that a given memory range is mapped encrypted
>> - * or decrypted.
>> - */
>> - notify_range_enc_status_changed(addr, numpages, enc);
>> -
>> return ret;
>> }
>>
>> --
>> 2.25.1
>>
>
next prev parent reply other threads:[~2022-02-21 19:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <Ygz88uacbwuTTNat@zn.tnic.mbx>
2022-02-16 16:04 ` [PATCH v10 21/45] x86/mm: Add support to validate memory when changing C-bit Brijesh Singh
2022-02-21 17:41 ` Kirill A. Shutemov
2022-02-21 18:06 ` Borislav Petkov
2022-02-21 19:54 ` Brijesh Singh [this message]
2022-02-09 18:09 [PATCH v10 00/45] Add AMD Secure Nested Paging (SEV-SNP) Guest Support Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 21/45] x86/mm: Add support to validate memory when changing C-bit Brijesh Singh
2022-02-10 16:48 ` Borislav Petkov
2022-02-11 14:55 ` Borislav Petkov
2022-02-11 17:27 ` Brijesh Singh
2022-02-13 12:15 ` Borislav Petkov
2022-02-13 14:50 ` Tom Lendacky
2022-02-13 17:21 ` Borislav Petkov
2022-02-15 12:43 ` Kirill A. Shutemov
2022-02-15 12:54 ` Borislav Petkov
2022-02-15 13:15 ` Kirill A. Shutemov
2022-02-15 14:41 ` Borislav Petkov
2022-02-16 13:32 ` Borislav Petkov
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