From: Brijesh Singh <brijesh.singh@amd.com>
To: <x86@kernel.org>, <linux-kernel@vger.kernel.org>,
<kvm@vger.kernel.org>, <linux-efi@vger.kernel.org>,
<platform-driver-x86@vger.kernel.org>,
<linux-coco@lists.linux.dev>, <linux-mm@kvack.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Joerg Roedel <jroedel@suse.de>,
Tom Lendacky <thomas.lendacky@amd.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Ard Biesheuvel <ardb@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
"Vitaly Kuznetsov" <vkuznets@redhat.com>,
Jim Mattson <jmattson@google.com>,
"Andy Lutomirski" <luto@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Sergio Lopez <slp@redhat.com>, Peter Gonda <pgonda@google.com>,
"Peter Zijlstra" <peterz@infradead.org>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
David Rientjes <rientjes@google.com>,
Dov Murik <dovmurik@linux.ibm.com>,
Tobin Feldman-Fitzthum <tobin@ibm.com>,
Borislav Petkov <bp@alien8.de>,
Michael Roth <michael.roth@amd.com>,
Vlastimil Babka <vbabka@suse.cz>,
"Kirill A . Shutemov" <kirill@shutemov.name>,
Andi Kleen <ak@linux.intel.com>,
"Dr . David Alan Gilbert" <dgilbert@redhat.com>,
<brijesh.ksingh@gmail.com>, <tony.luck@intel.com>,
<marcorr@google.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Venu Busireddy <venu.busireddy@oracle.com>,
Brijesh Singh <brijesh.singh@amd.com>
Subject: [PATCH v10 03/45] KVM: SVM: Create a separate mapping for the GHCB save area
Date: Wed, 9 Feb 2022 12:09:57 -0600 [thread overview]
Message-ID: <20220209181039.1262882-4-brijesh.singh@amd.com> (raw)
In-Reply-To: <20220209181039.1262882-1-brijesh.singh@amd.com>
From: Tom Lendacky <thomas.lendacky@amd.com>
The initial implementation of the GHCB spec was based on trying to keep
the register state offsets the same relative to the VM save area. However,
the save area for SEV-ES has changed within the hardware causing the
relation between the SEV-ES save area to change relative to the GHCB save
area.
This is the second step in defining the multiple save areas to keep them
separate and ensuring proper operation amongst the different types of
guests. Create a GHCB save area that matches the GHCB specification.
Reviewed-by: Venu Busireddy <venu.busireddy@oracle.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
arch/x86/include/asm/svm.h | 48 +++++++++++++++++++++++++++++++++++---
1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 3ce2e575a2de..5ff1fa364a31 100644
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -354,11 +354,51 @@ struct sev_es_save_area {
u64 x87_state_gpa;
} __packed;
+struct ghcb_save_area {
+ u8 reserved_1[203];
+ u8 cpl;
+ u8 reserved_2[116];
+ u64 xss;
+ u8 reserved_3[24];
+ u64 dr7;
+ u8 reserved_4[16];
+ u64 rip;
+ u8 reserved_5[88];
+ u64 rsp;
+ u8 reserved_6[24];
+ u64 rax;
+ u8 reserved_7[264];
+ u64 rcx;
+ u64 rdx;
+ u64 rbx;
+ u8 reserved_8[8];
+ u64 rbp;
+ u64 rsi;
+ u64 rdi;
+ u64 r8;
+ u64 r9;
+ u64 r10;
+ u64 r11;
+ u64 r12;
+ u64 r13;
+ u64 r14;
+ u64 r15;
+ u8 reserved_9[16];
+ u64 sw_exit_code;
+ u64 sw_exit_info_1;
+ u64 sw_exit_info_2;
+ u64 sw_scratch;
+ u8 reserved_10[56];
+ u64 xcr0;
+ u8 valid_bitmap[16];
+ u64 x87_state_gpa;
+} __packed;
+
#define GHCB_SHARED_BUF_SIZE 2032
struct ghcb {
- struct sev_es_save_area save;
- u8 reserved_save[2048 - sizeof(struct sev_es_save_area)];
+ struct ghcb_save_area save;
+ u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
@@ -369,6 +409,7 @@ struct ghcb {
#define EXPECTED_VMCB_SAVE_AREA_SIZE 740
+#define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1032
#define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
#define EXPECTED_GHCB_SIZE PAGE_SIZE
@@ -376,6 +417,7 @@ struct ghcb {
static inline void __unused_size_checks(void)
{
BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
+ BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
@@ -446,7 +488,7 @@ struct vmcb {
/* GHCB Accessor functions */
#define GHCB_BITMAP_IDX(field) \
- (offsetof(struct sev_es_save_area, field) / sizeof(u64))
+ (offsetof(struct ghcb_save_area, field) / sizeof(u64))
#define DEFINE_GHCB_ACCESSORS(field) \
static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
--
2.25.1
next prev parent reply other threads:[~2022-02-09 18:11 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 18:09 [PATCH v10 00/45] Add AMD Secure Nested Paging (SEV-SNP) Guest Support Brijesh Singh
2022-02-09 18:09 ` [PATCH v10 01/45] KVM: SVM: Define sev_features and vmpl field in the VMSA Brijesh Singh
2022-02-09 18:09 ` [PATCH v10 02/45] KVM: SVM: Create a separate mapping for the SEV-ES save area Brijesh Singh
2022-02-09 18:09 ` Brijesh Singh [this message]
2022-02-09 18:09 ` [PATCH v10 04/45] KVM: SVM: Update the SEV-ES save area mapping Brijesh Singh
2022-02-09 18:09 ` [PATCH v10 05/45] x86/boot: Introduce helpers for MSR reads/writes Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 06/45] x86/boot: Use MSR read/write helpers instead of inline assembly Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 07/45] x86/compressed/64: Detect/setup SEV/SME features earlier in boot Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 08/45] x86/sev: " Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 09/45] x86/mm: Extend cc_attr to include AMD SEV-SNP Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 10/45] x86/sev: Define the Linux specific guest termination reasons Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 11/45] x86/sev: Save the negotiated GHCB version Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 12/45] x86/sev: Check SEV-SNP features support Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 13/45] x86/sev: Add a helper for the PVALIDATE instruction Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 14/45] x86/sev: Check the vmpl level Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 15/45] x86/compressed: Add helper for validating pages in the decompression stage Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 16/45] x86/compressed: Register GHCB memory when SEV-SNP is active Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 17/45] x86/sev: " Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 18/45] x86/sev: Add helper for validating pages in early enc attribute changes Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 19/45] x86/kernel: Make the .bss..decrypted section shared in RMP table Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 20/45] x86/kernel: Validate ROM memory before accessing when SEV-SNP is active Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 21/45] x86/mm: Add support to validate memory when changing C-bit Brijesh Singh
2022-02-10 16:48 ` Borislav Petkov
2022-02-11 14:55 ` Borislav Petkov
2022-02-11 17:27 ` Brijesh Singh
2022-02-13 12:15 ` Borislav Petkov
2022-02-13 14:50 ` Tom Lendacky
2022-02-13 17:21 ` Borislav Petkov
2022-02-15 12:43 ` Kirill A. Shutemov
2022-02-15 12:54 ` Borislav Petkov
2022-02-15 13:15 ` Kirill A. Shutemov
2022-02-15 14:41 ` Borislav Petkov
2022-02-16 13:32 ` Borislav Petkov
2022-02-09 18:10 ` [PATCH v10 22/45] x86/sev: Use SEV-SNP AP creation to start secondary CPUs Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 23/45] x86/head/64: Re-enable stack protection Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 24/45] x86/compressed/acpi: Move EFI detection to helper Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 25/45] x86/compressed/acpi: Move EFI system table lookup " Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 26/45] x86/compressed/acpi: Move EFI config " Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 27/45] x86/compressed/acpi: Move EFI vendor " Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 28/45] x86/compressed/acpi: Move EFI kexec handling into common code Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 29/45] x86/boot: Add Confidential Computing type to setup_data Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 30/45] KVM: x86: Move lookup of indexed CPUID leafs to helper Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 31/45] x86/sev: Move MSR-based VMGEXITs for CPUID " Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 32/45] x86/compressed/64: Add support for SEV-SNP CPUID table in #VC handlers Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 33/45] x86/boot: Add a pointer to Confidential Computing blob in bootparams Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 34/45] x86/compressed: Add SEV-SNP feature detection/setup Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 35/45] x86/compressed: Use firmware-validated CPUID leaves for SEV-SNP guests Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 36/45] x86/compressed: Export and rename add_identity_map() Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 37/45] x86/compressed/64: Add identity mapping for Confidential Computing blob Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 38/45] x86/sev: Add SEV-SNP feature detection/setup Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 39/45] x86/sev: Use firmware-validated CPUID for SEV-SNP guests Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 40/45] x86/sev: Provide support for SNP guest request NAEs Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 41/45] x86/sev: Register SEV-SNP guest request platform device Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 42/45] virt: Add SEV-SNP guest driver Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 43/45] virt: sevguest: Add support to derive key Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 44/45] virt: sevguest: Add support to get extended report Brijesh Singh
2022-02-09 18:10 ` [PATCH v10 45/45] virt: sevguest: Add documentation for SEV-SNP CPUID Enforcement Brijesh Singh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220209181039.1262882-4-brijesh.singh@amd.com \
--to=brijesh.singh@amd.com \
--cc=ak@linux.intel.com \
--cc=ardb@kernel.org \
--cc=bp@alien8.de \
--cc=brijesh.ksingh@gmail.com \
--cc=dave.hansen@linux.intel.com \
--cc=dgilbert@redhat.com \
--cc=dovmurik@linux.ibm.com \
--cc=hpa@zytor.com \
--cc=jmattson@google.com \
--cc=jroedel@suse.de \
--cc=kirill@shutemov.name \
--cc=kvm@vger.kernel.org \
--cc=linux-coco@lists.linux.dev \
--cc=linux-efi@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=luto@kernel.org \
--cc=marcorr@google.com \
--cc=michael.roth@amd.com \
--cc=mingo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=pgonda@google.com \
--cc=platform-driver-x86@vger.kernel.org \
--cc=rientjes@google.com \
--cc=sathyanarayanan.kuppuswamy@linux.intel.com \
--cc=seanjc@google.com \
--cc=slp@redhat.com \
--cc=srinivas.pandruvada@linux.intel.com \
--cc=tglx@linutronix.de \
--cc=thomas.lendacky@amd.com \
--cc=tobin@ibm.com \
--cc=tony.luck@intel.com \
--cc=vbabka@suse.cz \
--cc=venu.busireddy@oracle.com \
--cc=vkuznets@redhat.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).