From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A267F37154 for ; Wed, 29 Nov 2023 15:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RgyRovia" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701270624; x=1732806624; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=+WmXrJbd+4V27ux01qGWHb6jKBIycuX+25UjSdydb/I=; b=RgyRoviavxYqyQwBVua1cbPjAfn7ABiGdA+Aox4xkPPVeZw+kcPvVPIH cxDMJk+BDWkIQjeKrxNrlBifEhdvbW4Af8W2+NRtL6YABH7wLGQr8I1XI RWzmS3o7b5NikU6TmttAeP0uXc27lncOrFM87Qz9a3y0EQ0PvgCX9rljB EzBYWpwCViJUdZWfji69HLX/6sYJRIEklzKpFTvvU5yEKwl+tocDnR1xi 7r+Z2xq8YCVORY5NlMa7fL3ebwrrWzhDlo6+iqskgSkS8zlKaBDXvLGrX l7R7vGi0l8ROLuOvdyve2DcbW3eWhFaZW1Rg6aNvLmCPY5Hj9XoL1/F1g g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="162830" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="162830" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 07:10:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="1016292536" X-IronPort-AV: E=Sophos;i="6.04,235,1695711600"; d="scan'208";a="1016292536" Received: from padamowi-mobl1.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.60.113]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 07:10:16 -0800 Received: by box.shutemov.name (Postfix, from userid 1000) id E10D010A424; Wed, 29 Nov 2023 18:10:12 +0300 (+03) Date: Wed, 29 Nov 2023 18:10:12 +0300 From: "kirill.shutemov@linux.intel.com" To: Michael Kelley Cc: "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "kys@microsoft.com" , "haiyangz@microsoft.com" , "wei.liu@kernel.org" , "decui@microsoft.com" , "luto@kernel.org" , "peterz@infradead.org" , "akpm@linux-foundation.org" , "urezki@gmail.com" , "hch@infradead.org" , "lstoakes@gmail.com" , "thomas.lendacky@amd.com" , "ardb@kernel.org" , "jroedel@suse.de" , "seanjc@google.com" , "rick.p.edgecombe@intel.com" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "linux-kernel@vger.kernel.org" , "linux-coco@lists.linux.dev" , "linux-hyperv@vger.kernel.org" , "linux-mm@kvack.org" Subject: Re: [PATCH v2 0/8] x86/coco: Mark CoCo VM pages not present when changing encrypted state Message-ID: <20231129151012.4un33hvk4nrsicou@box> References: <20231121212016.1154303-1-mhklinux@outlook.com> <20231124100627.avltdnuhminwuzax@box> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Nov 28, 2023 at 07:12:33PM +0000, Michael Kelley wrote: > From: kirill.shutemov@linux.intel.com Sent: Friday, November 24, 2023 2:06 AM > > > > On Tue, Nov 21, 2023 at 01:20:08PM -0800, mhkelley58@gmail.com wrote: > > > From: Michael Kelley > > > > > > In a CoCo VM when a page transitions from encrypted to decrypted, or vice > > > versa, attributes in the PTE must be updated *and* the hypervisor must > > > be notified of the change. > > > > Strictly speaking it is not true for TDX. Conversion to shared can be > > implicit: set shared bit and touch the page will do the conversion. MapGPA > > is optional. > > Interesting. Given that, is there a reason to use the explicit > hypervisor callbacks in for private->shared transitions in > __set_mem_enc_pgtable()? It probably doesn't have direct relevance > to this patch series, but I'm just trying to understand the tradeoffs of > the implicit vs. explicit approach. And am I correct that > shared->private transitions must use the explicit approach? It must be explicit in sense, that the memory has to be accepted before use. MapGPA() is still optional. I don't like this implicit tricks. I spent a lot of time debugging an issue that was obscured by this semantics. But I think it is going to say :/ > > > Because there are two separate steps, there's > > > a window where the settings are inconsistent. Normally the code that > > > initiates the transition (via set_memory_decrypted() or > > > set_memory_encrypted()) ensures that the memory is not being accessed > > > during a transition, so the window of inconsistency is not a problem. > > > However, the load_unaligned_zeropad() function can read arbitrary memory > > > pages at arbitrary times, which could read a transitioning page during > > > the window. In such a case, CoCo VM specific exceptions are taken > > > (depending on the CoCo architecture in use). Current code in those > > > exception handlers recovers and does "fixup" on the result returned by > > > load_unaligned_zeropad(). Unfortunately, this exception handling can't > > > work in paravisor scenarios (TDX Paritioning and SEV-SNP in vTOM mode) > > > if the exceptions are routed to the paravisor. The paravisor can't > > > do load_unaligned_zeropad() fixup, so the exceptions would need to > > > be forwarded from the paravisor to the Linux guest, but there are > > > no architectural specs for how to do that. > > > > Hm. Can't we inject #PF (or #GP) into L2 if #VE/#VC handler in L1 sees > > cross-page access to shared memory while no fixup entry for the page in > > L1. It would give L2 chance to handle the situation in a transparent way. > > > > Maybe I miss something, I donno. > > I'm recounting what the Hyper-V paravisor folks say without knowing all the > details. :-( But it seems like any kind of forwarding scheme needs to be a > well-defined contract that would work for both TDX and SEV-SNP. The > paravisor in L1 might or might not be Linux-based, so the contract must be OS > independent. And the L2 guest might or might not be Linux, so there's > potential for some other kind of error to be confused with a Linux > load_unaligned_zeropad() reference. Okay, fair enough. I have hard time reasoning if it is okay for L2 which is not Linux. -- Kiryl Shutsemau / Kirill A. Shutemov