From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADE3A28BA88 for ; Tue, 29 Jul 2025 15:23:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753802596; cv=none; b=aHyabtIN1ZOj2Gvp5jtpe8ukNDmJyGqbAUCoTKdjn7DSLIz4nt/ccHfbx/ytruYocOPWssDUMOgpLCr3G+LgdgMCGjwp10L6X+5CWoxGlkelBjwtpdgvnDAJusnOXHSY+4/dE1XeSKQEgMdA63940AJLJhZsPl1lA/HMCLhQ4gY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753802596; c=relaxed/simple; bh=UdF7+MyEQN4lowG4g1QHvKAmtAPL0t7ARw6Hx2CJGp8=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RUnc7PWZT9kbaxKo9bB7vQwT+jP2CGkCBhHh5GVFmayWzNB6wz1BKGXhpWx3RkmYBjFS/KOnvC88u9EwuKC1k2eayuZrerOxXBnANHR/9NTF0/uXk47i1WjHtWem/ohBXZwDw2BLvTeenN2+5r45Fg9peuCZ7T6b11jSUTxTiBI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4brzX63S5fz6JB0Y; Tue, 29 Jul 2025 23:19:02 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id D34D1140372; Tue, 29 Jul 2025 23:23:12 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 29 Jul 2025 17:23:12 +0200 Date: Tue, 29 Jul 2025 16:23:10 +0100 From: Jonathan Cameron To: Dan Williams CC: , , , , , , Ilpo =?ISO-8859-1?Q?J=E4rvinen?= , Samuel Ortiz , "Xu Yilun" Subject: Re: [PATCH v4 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration Message-ID: <20250729162310.00001fbb@huawei.com> In-Reply-To: <20250717183358.1332417-7-dan.j.williams@intel.com> References: <20250717183358.1332417-1-dan.j.williams@intel.com> <20250717183358.1332417-7-dan.j.williams@intel.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To frapeml500008.china.huawei.com (7.182.85.71) On Thu, 17 Jul 2025 11:33:54 -0700 Dan Williams wrote: > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure, > enumerates new link capabilities and status added for Gen 6 devices. One > of the link details enumerated in that register block is the "Segment > Captured" status in the Device Status 3 register. That status is > relevant for enabling IDE (Integrity & Data Encryption) whereby > Selective IDE streams can be limited to a given Requester ID range > within a given segment. >=20 > If a device has captured its Segment value then it knows that PCIe Flit > Mode is enabled via all links in the path that a configuration write > traversed. IDE establishment requires that "Segment Base" in > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be > programmed if the RID association mechanism is in effect. >=20 > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to > setup the segment base when using the RID association facility, but no > known deployments today depend on this. >=20 > Cc: Lukas Wunner > Cc: Ilpo J=E4rvinen > Cc: Bjorn Helgaas > Cc: Samuel Ortiz > Cc: Alexey Kardashevskiy > Cc: Xu Yilun > Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 1b991a88c19c..2d49a4786a9f 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -751,6 +751,7 @@ > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ > #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ > #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT > @@ -1227,6 +1228,12 @@ > /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYP= E */ > #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DIS= C_RSP_3_TYPE > =20 > +/* Device 3 Extended Capability */ > +#define PCI_DEV3_CAP 0x4 /* Device 3 Capabilities Register */ Similar to earlier cases I'd make these 0x04 etc just to copy local style += match spec. > +#define PCI_DEV3_CTL 0x8 /* Device 3 Control Register */ > +#define PCI_DEV3_STA 0xc /* Device 3 Status Register */ > +#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-m= ode detected) */ > + > /* Compute Express Link (CXL r3.1, sec 8.1.5) */ > #define PCI_DVSEC_CXL_PORT 3 > #define PCI_DVSEC_CXL_PORT_CTL 0x0c