From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D6E8293C58 for ; Tue, 29 Jul 2025 16:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753805224; cv=none; b=nBQs/vtlV3wXgUjWDN7tutTiEbq3aQqRLK3GMuHBH5j0c8CTIoBowS9Bqg5enGZILtUA0aoV0ooiH5kIQZokzm2vj9liPxdSw5CX7oe1UuVike59bMR/07De6zgU+/49ZYnGZmdCEp1Yrmm/xezHrTGF6POYr+kSe9zIoj5qEgU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753805224; c=relaxed/simple; bh=NPEcovrwDo43N0AHF4g6DbPS5QsdPMou8/qukFuHUdE=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=E/VmwBhLDGGM+gT99xF1sR+3BolfvXEV3xsW9yAYIMTFVlUI281RXbyJrnft7ji+b4oI1rlOFNXo9OzuzQQ5VTegVR1pcxGIjFGkKsrub3tzoTTiflzIXrQ8bgAnXTT8JMtd8VRIfOcad0v+JKa4lFrm2ty7e9iBVFQohmkPdCA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bs0Yd20w7z6H8fN; Wed, 30 Jul 2025 00:05:25 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 0130F1402F4; Wed, 30 Jul 2025 00:07:00 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 29 Jul 2025 18:06:59 +0200 Date: Tue, 29 Jul 2025 17:06:57 +0100 From: Jonathan Cameron To: Dan Williams CC: , , , , , , Samuel Ortiz , Xu Yilun , Suzuki K Poulose , Aneesh Kumar K.V Subject: Re: [PATCH v4 10/10] samples/devsec: Add sample IDE establishment Message-ID: <20250729170657.00005638@huawei.com> In-Reply-To: <20250717183358.1332417-11-dan.j.williams@intel.com> References: <20250717183358.1332417-1-dan.j.williams@intel.com> <20250717183358.1332417-11-dan.j.williams@intel.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To frapeml500008.china.huawei.com (7.182.85.71) On Thu, 17 Jul 2025 11:33:58 -0700 Dan Williams wrote: > Exercise common setup and teardown flows for a sample platform TSM > driver that implements the TSM 'connect' and 'disconnect' flows. > > This is both a template for platform specific implementations and a > simple integration test for the PCI core infrastructure + ABI. > > Cc: Bjorn Helgaas > Cc: Lukas Wunner > Cc: Samuel Ortiz > Cc: Alexey Kardashevskiy > Cc: Xu Yilun > Cc: Suzuki K Poulose > Cc: "Aneesh Kumar K.V" > Signed-off-by: Dan Williams One really trivial comment inline. > diff --git a/samples/devsec/tsm.c b/samples/devsec/tsm.c > index a4705212a7e4..b93396ca0c92 100644 > --- a/samples/devsec/tsm.c > +++ b/samples/devsec/tsm.c > > static void devsec_tsm_disconnect(struct pci_dev *pdev) > { > + struct pci_ide *ide; > + unsigned long i; > + > + for_each_set_bit(i, devsec_stream_ids, NR_TSM_STREAMS) > + if (devsec_streams[i]->pdev == pdev) > + break; > + > + if (i >= NR_TSM_STREAMS) pet irritation - why imply cases that can't occur. if (i == NR_TSM_STREAMS) > + return; > + > + ide = devsec_streams[i]; > + devsec_streams[i] = NULL; > + pci_ide_stream_release(ide); > + clear_bit(i, devsec_stream_ids); > } > > static struct pci_tsm_ops devsec_pci_ops = {