From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 821412D3ECE for ; Thu, 11 Sep 2025 23:56:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757635016; cv=none; b=D25iGoMmvk1c4O4gUBtS8Meiol8h/RchSRGIpq3CflsF7/309GtkzbIxh9s5rOs8Avr/t4KwaB/4M/iZ4bXOyid9qFjZCO2J873pOVTBq8CHecwTxZL/08VbaihZ2iyifZG7dNfvjuO2LwZfmab508xDt+1no+TVoTgfPDR9bks= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757635016; c=relaxed/simple; bh=2dzWwt4zpZM5EC+MjzgWRnu2cYCHGK0L/hvc78Ekzws=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=twUW5wJd6oroP7Y/EsD58l1Q2fkB06xABMSVcNLvDwsW273CtIu5O5yJ0XHhZ+y4hyEnEqDuuhYyyZ/Q60NHROtD/dexoplWag9Ra8RR22ZsG35PyWu0ofVFexAWV1VmKKlXNTb+NbYEvJzt8nu3UVWnXnCQzCn2B/XgPlxs6yg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LNVzt9xJ; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LNVzt9xJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757635015; x=1789171015; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2dzWwt4zpZM5EC+MjzgWRnu2cYCHGK0L/hvc78Ekzws=; b=LNVzt9xJWRYmAiljg5p8biUXMKeCUP+IlDGaneBxOxbkLmGMHB8Gx1ri moNl4s2lvweCDGUw5hxMXQDxrKwj7UKddcQPJ0+vuNk0Nelgk64sq4apa bPfT4SsQEb2pob3Htuw+05imuMsSCjVHmo/BIOSCBldXcdqqcXwEVGcC1 BQcXJyeNh6sZY3ZV7OiGQf/hak+TwHx6Q4YjA/CKeusfPyVkyS4MX6pG9 1oiRnWdJBaHdwcI5qOeGCyrqgflkp0d3JodFMLUXF+oIf4jHCWuv3vZUI eFMwdO7TmiYbolH+Eu2VBDgAbaIBeQxvy5MlmXfllpmBLxhrgIz9Ef897 g==; X-CSE-ConnectionGUID: zGvM7K7zRTC7fo+FtxcrKA== X-CSE-MsgGUID: +6OLooJGQ1iRZDsTvtcWzw== X-IronPort-AV: E=McAfee;i="6800,10657,11550"; a="70598741" X-IronPort-AV: E=Sophos;i="6.18,258,1751266800"; d="scan'208";a="70598741" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 16:56:50 -0700 X-CSE-ConnectionGUID: U47Jbi1FSzu40xr8hPR8Kg== X-CSE-MsgGUID: 8z8wGZqLTdGUtdzTrrpYQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,258,1751266800"; d="scan'208";a="173393532" Received: from dwillia2-desk.jf.intel.com ([10.88.27.145]) by fmviesa007.fm.intel.com with ESMTP; 11 Sep 2025 16:56:49 -0700 From: Dan Williams To: linux-pci@vger.kernel.org, linux-coco@lists.linux.dev Cc: gregkh@linuxfoundation.org, bhelgaas@google.com, lukas@wunner.de, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Samuel Ortiz , Alexey Kardashevskiy , Xu Yilun , Jonathan Cameron Subject: [PATCH resend v6 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration Date: Thu, 11 Sep 2025 16:56:43 -0700 Message-ID: <20250911235647.3248419-7-dan.j.williams@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250911235647.3248419-1-dan.j.williams@intel.com> References: <20250911235647.3248419-1-dan.j.williams@intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCIe r7.0 Section 7.7.9 Device 3 Extended Capability Structure, defines the canonical location for determining the Flit Mode of a device. This status is a dependency for PCIe IDE enabling. Add a new fm_enabled flag to 'struct pci_dev'. Cc: Lukas Wunner Cc: Ilpo Järvinen Cc: Bjorn Helgaas Cc: Samuel Ortiz Cc: Alexey Kardashevskiy Cc: Xu Yilun Acked-by: Bjorn Helgaas Reviewed-by: Jonathan Cameron Signed-off-by: Dan Williams --- drivers/pci/probe.c | 12 ++++++++++++ include/linux/pci.h | 1 + include/uapi/linux/pci_regs.h | 7 +++++++ 3 files changed, 20 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 7207f9a76a3e..6e308199001c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2271,6 +2271,17 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign) return 0; } +static void pci_dev3_init(struct pci_dev *pdev) +{ + u16 cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DEV3); + u32 val = 0; + + if (!cap) + return; + pci_read_config_dword(pdev, cap + PCI_DEV3_STA, &val); + pdev->fm_enabled = !!(val & PCI_DEV3_STA_SEGMENT); +} + /** * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable * @dev: PCI device to query @@ -2642,6 +2653,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_doe_init(dev); /* Data Object Exchange */ pci_tph_init(dev); /* TLP Processing Hints */ pci_rebar_init(dev); /* Resizable BAR */ + pci_dev3_init(dev); /* Device 3 capabilities */ pci_ide_init(dev); /* Link Integrity and Data Encryption */ pcie_report_downtraining(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 78c1e208d441..d3880a4f175e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -449,6 +449,7 @@ struct pci_dev { unsigned int pasid_enabled:1; /* Process Address Space ID */ unsigned int pri_enabled:1; /* Page Request Interface */ unsigned int tph_enabled:1; /* TLP Processing Hints */ + unsigned int fm_enabled:1; /* Flit Mode (segment captured) */ unsigned int is_managed:1; /* Managed via devres */ unsigned int is_msi_managed:1; /* MSI release via devres installed */ unsigned int needs_freset:1; /* Requires fundamental reset */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 9d30307a3499..b6ea1ffbf489 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -752,6 +752,7 @@ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ #define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ +#define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT @@ -1236,6 +1237,12 @@ /* Deprecated old name, replaced with PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE */ #define PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL PCI_DOE_DATA_OBJECT_DISC_RSP_3_TYPE +/* Device 3 Extended Capability */ +#define PCI_DEV3_CAP 0x04 /* Device 3 Capabilities Register */ +#define PCI_DEV3_CTL 0x08 /* Device 3 Control Register */ +#define PCI_DEV3_STA 0x0c /* Device 3 Status Register */ +#define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mode detected) */ + /* Compute Express Link (CXL r3.1, sec 8.1.5) */ #define PCI_DVSEC_CXL_PORT 3 #define PCI_DVSEC_CXL_PORT_CTL 0x0c -- 2.51.0