From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0077826B942 for ; Thu, 11 Sep 2025 23:56:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757635017; cv=none; b=iPpeqWLKLeGODFztfxyZNQpFs/06WTRz6O35Pg8txF418K/jEtae7V8dMvZD7jVYtjrbcYI7JMHna6DN4J7nqf4mfBKLYBncbp90jDVhpjo6EdVa+Irq/WKxsi4N/W6wEJlbMh2tX6zumNgxdDGb1/A44EP/Y9gi+4D//YYLyYE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757635017; c=relaxed/simple; bh=bjteZad0h7nv1n7j0NcNq+YwGCKnPjrVfJjR1E/mVjg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FCeG7ft6LhSRO7bqPab67+3ocx4+HIgro5QHvY4BMlT/BT8eWAUeNZ5sPH5SckM5vMsyhhCTqLb5LZebgCAu8rv2bRDREjXxnocSacTiwx0ExLiT9mFP3h5FbF7ieBUrd5Zq/y/3VCKEmxsreRWLOeZ0cAjHrXiupsieJrUVdEA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ERGxMCMw; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ERGxMCMw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757635016; x=1789171016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bjteZad0h7nv1n7j0NcNq+YwGCKnPjrVfJjR1E/mVjg=; b=ERGxMCMwFAdw6gkpEK3CTjeuF1IBOEyN3iSRf2XAciEfNQKlQXcq/UPc vdjDCQRhWVUqt4qzu6V0I6KYAgZAkar8tlqkFvcdv0b1ogTox+zNcZV3h ih0df2vdk/FvRHoz+81AeKfsBmlfmBLkVUPfOYZpIWz8UDQEU9N9d/XPY 9VCk3r7hBgxzjkCqNuPmr63wHlr88Afmlvy+DeaA8xyZSoOcubN6W0yH5 DMb8QXyqB0PMEkHRcWF5ZzlLEunaiSLawnUXgKaDC7UAsmQx5OVzSUVwI xtWaYbCpORp3+BWY7di0Bfx33ZAtf+/asWBmgdgbiQHu6vI2o1yl9RQJV A==; X-CSE-ConnectionGUID: gUGd7vA1Q2OlTJtKNXujBg== X-CSE-MsgGUID: eXx8ARejS6CecfBCK6evaA== X-IronPort-AV: E=McAfee;i="6800,10657,11550"; a="70598756" X-IronPort-AV: E=Sophos;i="6.18,258,1751266800"; d="scan'208";a="70598756" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 16:56:51 -0700 X-CSE-ConnectionGUID: 6kiQRhRGTvqQd/lmHLXQ/Q== X-CSE-MsgGUID: azbLreqrQ1amtpDHf3Djjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,258,1751266800"; d="scan'208";a="173393538" Received: from dwillia2-desk.jf.intel.com ([10.88.27.145]) by fmviesa007.fm.intel.com with ESMTP; 11 Sep 2025 16:56:50 -0700 From: Dan Williams To: linux-pci@vger.kernel.org, linux-coco@lists.linux.dev Cc: gregkh@linuxfoundation.org, bhelgaas@google.com, lukas@wunner.de, Samuel Ortiz , Alexey Kardashevskiy , Xu Yilun , Jonathan Cameron Subject: [PATCH resend v6 08/10] PCI/IDE: Report available IDE streams Date: Thu, 11 Sep 2025 16:56:45 -0700 Message-ID: <20250911235647.3248419-9-dan.j.williams@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250911235647.3248419-1-dan.j.williams@intel.com> References: <20250911235647.3248419-1-dan.j.williams@intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The limited number of link-encryption (IDE) streams that a given set of host bridges supports is a platform specific detail. Provide pci_ide_init_nr_streams() as a generic facility for either platform TSM drivers, or PCI core native IDE, to report the number available streams. After invoking pci_ide_init_nr_streams() an "available_secure_streams" attribute appears in PCI host bridge sysfs to convey that count. Introduce a device-type, @pci_host_bridge_type, now that both a release method and sysfs attribute groups are being specified for all 'struct pci_host_bridge' instances. Cc: Bjorn Helgaas Cc: Lukas Wunner Cc: Samuel Ortiz Cc: Alexey Kardashevskiy Cc: Xu Yilun Acked-by: Bjorn Helgaas Reviewed-by: Jonathan Cameron Signed-off-by: Dan Williams --- .../ABI/testing/sysfs-devices-pci-host-bridge | 12 ++++ drivers/pci/ide.c | 59 +++++++++++++++++++ drivers/pci/pci.h | 3 + drivers/pci/probe.c | 12 +++- include/linux/pci.h | 8 +++ 5 files changed, 93 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-devices-pci-host-bridge b/Documentation/ABI/testing/sysfs-devices-pci-host-bridge index 2c66e5bb2bf8..b91ec3450811 100644 --- a/Documentation/ABI/testing/sysfs-devices-pci-host-bridge +++ b/Documentation/ABI/testing/sysfs-devices-pci-host-bridge @@ -31,3 +31,15 @@ Description: platform specific pool of stream resources shared by the Root Ports in a host bridge. See /sys/devices/pciDDDD:BB entry for details about the DDDD:BB format. + +What: pciDDDD:BB/available_secure_streams +Contact: linux-pci@vger.kernel.org +Description: + (RO) When a host bridge has Root Ports that support PCIe IDE + (link encryption and integrity protection) there may be a + limited number of Selective IDE Streams that can be used for + establishing new end-to-end secure links. This attribute + decrements upon secure link setup, and increments upon secure + link teardown. The in-use stream count is determined by counting + stream symlinks. See /sys/devices/pciDDDD:BB entry for details + about the DDDD:BB format. diff --git a/drivers/pci/ide.c b/drivers/pci/ide.c index 608ce79d830f..eb6e146e6fb5 100644 --- a/drivers/pci/ide.c +++ b/drivers/pci/ide.c @@ -519,3 +519,62 @@ void pci_ide_stream_disable(struct pci_dev *pdev, struct pci_ide *ide) settings->enable = 0; } EXPORT_SYMBOL_GPL(pci_ide_stream_disable); + +static ssize_t available_secure_streams_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_host_bridge *hb = to_pci_host_bridge(dev); + int avail; + + if (!hb->nr_ide_streams) + return -ENXIO; + + avail = hb->nr_ide_streams - + bitmap_weight(hb->ide_stream_map, hb->nr_ide_streams); + return sysfs_emit(buf, "%d\n", avail); +} +static DEVICE_ATTR_RO(available_secure_streams); + +static struct attribute *pci_ide_attrs[] = { + &dev_attr_available_secure_streams.attr, + NULL +}; + +static umode_t pci_ide_attr_visible(struct kobject *kobj, struct attribute *a, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct pci_host_bridge *hb = to_pci_host_bridge(dev); + + if (a == &dev_attr_available_secure_streams.attr) + if (!hb->nr_ide_streams) + return 0; + + return a->mode; +} + +struct attribute_group pci_ide_attr_group = { + .attrs = pci_ide_attrs, + .is_visible = pci_ide_attr_visible, +}; + +/** + * pci_ide_init_nr_streams() - sets size of the pool of IDE Stream resources + * @hb: host bridge boundary for the stream pool + * @nr: number of streams + * + * Platform PCI init and/or expert test module use only. Enable IDE + * Stream establishment by setting the number of stream resources + * available at the host bridge. Platform init code must set this before + * the first pci_ide_stream_alloc() call. + * + * The "PCI_IDE" symbol namespace is required because this is typically + * a detail that is settled in early PCI init. I.e. this export is not + * for endpoint drivers. + */ +void pci_ide_init_nr_streams(struct pci_host_bridge *hb, u8 nr) +{ + hb->nr_ide_streams = nr; + sysfs_update_group(&hb->dev.kobj, &pci_ide_attr_group); +} +EXPORT_SYMBOL_NS_GPL(pci_ide_init_nr_streams, "PCI_IDE"); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0e24262aa4ba..22e0256a10ba 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -521,8 +521,11 @@ static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } #ifdef CONFIG_PCI_IDE void pci_ide_init(struct pci_dev *dev); +extern struct attribute_group pci_ide_attr_group; +#define PCI_IDE_ATTR_GROUP (&pci_ide_attr_group) #else static inline void pci_ide_init(struct pci_dev *dev) { } +#define PCI_IDE_ATTR_GROUP NULL #endif #ifdef CONFIG_PCI_TSM diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6e308199001c..cc77020aa021 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -640,6 +640,16 @@ static void pci_release_host_bridge_dev(struct device *dev) kfree(bridge); } +static const struct attribute_group *pci_host_bridge_groups[] = { + PCI_IDE_ATTR_GROUP, + NULL +}; + +static const struct device_type pci_host_bridge_type = { + .groups = pci_host_bridge_groups, + .release = pci_release_host_bridge_dev, +}; + static void pci_init_host_bridge(struct pci_host_bridge *bridge) { INIT_LIST_HEAD(&bridge->windows); @@ -659,6 +669,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge) bridge->native_dpc = 1; bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; bridge->native_cxl_error = 1; + bridge->dev.type = &pci_host_bridge_type; device_initialize(&bridge->dev); } @@ -672,7 +683,6 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) return NULL; pci_init_host_bridge(bridge); - bridge->dev.release = pci_release_host_bridge_dev; return bridge; } diff --git a/include/linux/pci.h b/include/linux/pci.h index 45360ba87538..3a71f30211a5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -670,6 +670,14 @@ void pci_set_host_bridge_release(struct pci_host_bridge *bridge, void (*release_fn)(struct pci_host_bridge *), void *release_data); +#ifdef CONFIG_PCI_IDE +void pci_ide_init_nr_streams(struct pci_host_bridge *hb, u8 nr); +#else +static inline void pci_ide_init_nr_streams(struct pci_host_bridge *hb, u8 nr) +{ +} +#endif + int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ -- 2.51.0