Re: [PATCH 2/6] PCI/IDE: Add Address Association Register setup for downstream MMIO

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Wed, 5 Nov 2025 15:04:05 -0800
dan.j.williams@intel.com wrote:

> Jonathan Cameron wrote:
> > On Tue,  4 Nov 2025 20:00:51 -0800
> > Dan Williams <dan.j.williams@intel.com> wrote:
> >   
> > > From: Xu Yilun <yilun.xu@linux.intel.com>
> > > 
> > > The address ranges for downstream Address Association Registers need to
> > > cover memory addresses for all functions (PFs/VFs/downstream devices)
> > > managed by a Device Security Manager (DSM). The proposed solution is get
> > > the memory (32-bit only) range and prefetchable-memory (64-bit capable)
> > > range from the immediate ancestor downstream port (either the direct-attach
> > > RP or deepest switch port when switch attached).
> > > 
> > > Similar to RID association, address associations will be set by default if
> > > hardware sets 'Number of Address Association Register Blocks' in the
> > > 'Selective IDE Stream Capability Register' to a non-zero value. TSM drivers
> > > can opt-out of the settings by zero'ing out unwanted / unsupported address
> > > ranges. E.g. TDX Connect only supports prefetachable (64-bit capable)
> > > memory ranges for the Address Association setting.
> > > 
> > > If the immediate downstream port provides both a memory range and
> > > prefetchable-memory range, but the IDE partner port only provides 1 Address
> > > Association Register block then the TSM driver can pick which range to
> > > associate, or let the PCI core prioritize memory.
> > > 
> > > Note, the Address Association Register setup for upstream requests is still
> > > uncertain so is not included.
> > > 
> > > Co-developed-by: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
> > > Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@kernel.org>
> > > Co-developed-by: Arto Merilainen <amerilainen@nvidia.com>
> > > Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
> > > Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
> > > Co-developed-by: Dan Williams <dan.j.williams@intel.com>
> > > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> > > ---
> > >  include/linux/pci-ide.h |  27 ++++++++++
> > >  include/linux/pci.h     |   5 ++
> > >  drivers/pci/ide.c       | 115 ++++++++++++++++++++++++++++++++++++----
> > >  3 files changed, 138 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h
> > > index d0f10f3c89fc..55283c8490e4 100644
> > > --- a/include/linux/pci-ide.h
> > > +++ b/include/linux/pci-ide.h
> > > @@ -28,6 +28,9 @@ enum pci_ide_partner_select {
> > >   * @rid_start: Partner Port Requester ID range start
> > >   * @rid_end: Partner Port Requester ID range end
> > >   * @stream_index: Selective IDE Stream Register Block selection
> > > + * @mem_assoc: PCI bus memory address association for targeting peer partner  
> > 
> > The text above about TDX only support prefetchable to me suggestions this
> > is optional so should be marked so like pref_assoc?  
> 
> Maybe... I think I was more considering the fact that PCI compliant
> devices always have a 32-bit MMIO range. Given both are optional it
> might be better to detail that in the Description section:
> 
> diff --git a/include/linux/pci-ide.h b/include/linux/pci-ide.h
> index 40f0be185120..37a1ad9501b0 100644
> --- a/include/linux/pci-ide.h
> +++ b/include/linux/pci-ide.h
> @@ -29,13 +29,18 @@ enum pci_ide_partner_select {
>   * @rid_end: Partner Port Requester ID range end
>   * @stream_index: Selective IDE Stream Register Block selection
>   * @mem_assoc: PCI bus memory address association for targeting peer partner
> - * @pref_assoc: (optional) PCI bus prefetchable memory address association for
> + * @pref_assoc: PCI bus prefetchable memory address association for
>   *		targeting peer partner
>   * @default_stream: Endpoint uses this stream for all upstream TLPs regardless of
>   *		    address and RID association registers
>   * @setup: flag to track whether to run pci_ide_stream_teardown() for this
>   *	   partner slot
>   * @enable: flag whether to run pci_ide_stream_disable() for this partner slot
> + *
> + * By default, pci_ide_stream_alloc() initializes @mem_assoc and @pref_assoc
> + * with the immediate ancestor downstream port memory ranges (i.e. Type 1
> + * Configuration Space Header values). Caller may zero size ({0, -1}) the range
> + * to drop it from consideration at pci_ide_stream_setup() time.
>   */
That does the job. Thanks,

>  struct pci_ide_partner {
>  	u16 rid_start;