From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CDB2263C91 for ; Mon, 17 Nov 2025 02:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763347148; cv=none; b=WKo6nB0k/OU3AJDHZKsZxdkqWNoQBK0yIqc8Ghg1XM5bxMF8Z+2Ww/mcbOT0ltzNaxlRQRxtU9/70/yT2CjWQEQa/KHsjCLgdVKtZ28Vfsg8kucojpQMoqbJDWdrQM2SR821LFSU0z3QHGZU6/l6Ez79y89BOirMtJ45ySYQuLs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763347148; c=relaxed/simple; bh=1myzAhFF47JneeHorRvc+LNCA5N/wiuGMhgNApYfCJA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Hp+44jPv9I6/5vwKtwsPXUmnT4KKrwFACfFwDvmuWJJt1jmZNUKOQOOJpV9cYly5AKEeQOQWj4BUi01vAJeDBTiVLzNiRPKhnuc2+WuNMm8V+ZEPpLiWa30dxqnsj3PTF16EglJ2FyiR3hTa49bDn6uv/kMBs4a56KJa0AkXVaE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XWtzSNj2; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XWtzSNj2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763347148; x=1794883148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1myzAhFF47JneeHorRvc+LNCA5N/wiuGMhgNApYfCJA=; b=XWtzSNj2mxipK9nq6VW60K1ZzKkcrvT5ij1P0A9t9my8dq8/kp0yqhr4 eaeeDJF+YvRwlYjusWLjsBlRBkwIYSPSPeF7NtZhg4sVCWahxJM7c9iEO Q4sUb5sBWHyfdXErpOGlDtDV8eHvWzVP3z15ddMmGbvfLdJGLTiR3XBjm OvAyuX6sQWwAgcN8WVyJuawrUuko8oGdSkLyFEjS+PXkSNQszbu5pfPrV oSD8DaZYRZCDqupXDGKucrfZ4MEnnFNAAouASByyOcK1mVYEF02YnJeLg P6gRTZYMWpG/qbu+B2PqchHvjef4NvJZwKd7XUgNBoFexPDFNnkN1Lbqt A==; X-CSE-ConnectionGUID: JjLzIjvfRnihgE5PlyO9cg== X-CSE-MsgGUID: m7pMvd8iRX+LpEl7bTS5qw== X-IronPort-AV: E=McAfee;i="6800,10657,11615"; a="82729600" X-IronPort-AV: E=Sophos;i="6.19,310,1754982000"; d="scan'208";a="82729600" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2025 18:39:08 -0800 X-CSE-ConnectionGUID: VTJ68gS7RJOlP4MVFQabUQ== X-CSE-MsgGUID: 1dD9Jf/QQa6sw3OFk2geNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,310,1754982000"; d="scan'208";a="227658477" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165]) by orviesa001.jf.intel.com with ESMTP; 16 Nov 2025 18:39:03 -0800 From: Xu Yilun To: linux-coco@lists.linux.dev, linux-pci@vger.kernel.org Cc: chao.gao@intel.com, dave.jiang@intel.com, baolu.lu@linux.intel.com, yilun.xu@linux.intel.com, yilun.xu@intel.com, zhenzhong.duan@intel.com, kvm@vger.kernel.org, rick.p.edgecombe@intel.com, dave.hansen@linux.intel.com, dan.j.williams@intel.com, kas@kernel.org, x86@kernel.org Subject: [PATCH v1 20/26] coco/tdx-host: Add a helper to exchange SPDM messages through DOE Date: Mon, 17 Nov 2025 10:23:04 +0800 Message-Id: <20251117022311.2443900-21-yilun.xu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251117022311.2443900-1-yilun.xu@linux.intel.com> References: <20251117022311.2443900-1-yilun.xu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Zhenzhong Duan TDX host uses this function to exchange TDX Module encrypted data with devices via SPDM. It is unfortunate that TDX passes raw DOE frames with headers included and the PCI DOE core wants payloads separated from headers. This conversion code is about the same amount of work as teaching the PCI DOE driver to support raw frames. Unless and until another raw frame use case shows up, just do this conversion in the TDX TSM driver. Signed-off-by: Zhenzhong Duan Co-developed-by: Xu Yilun Signed-off-by: Xu Yilun Signed-off-by: Dan Williams Reviewed-by: Jonathan Cameron --- drivers/virt/coco/tdx-host/tdx-host.c | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-host/tdx-host.c index 3cd19966a61b..f0151561e00e 100644 --- a/drivers/virt/coco/tdx-host/tdx-host.c +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -5,10 +5,12 @@ * Copyright (C) 2025 Intel Corporation */ +#include #include #include #include #include +#include #include #include #include @@ -41,6 +43,65 @@ static struct tdx_link *to_tdx_link(struct pci_tsm *tsm) return container_of(tsm, struct tdx_link, pci.base_tsm); } +#define PCI_DOE_DATA_OBJECT_HEADER_1_OFFSET 0 +#define PCI_DOE_DATA_OBJECT_HEADER_2_OFFSET 4 +#define PCI_DOE_DATA_OBJECT_HEADER_SIZE 8 +#define PCI_DOE_DATA_OBJECT_PAYLOAD_OFFSET PCI_DOE_DATA_OBJECT_HEADER_SIZE + +#define PCI_DOE_PROTOCOL_SECURE_SPDM 2 + +static int __maybe_unused tdx_spdm_msg_exchange(struct tdx_link *tlink, + void *request, size_t request_sz, + void *response, size_t response_sz) +{ + struct pci_dev *pdev = tlink->pci.base_tsm.pdev; + void *req_pl_addr, *resp_pl_addr; + size_t req_pl_sz, resp_pl_sz; + u32 data, len; + u16 vendor; + u8 type; + int ret; + + /* + * pci_doe() accept DOE PAYLOAD only but request carries DOE HEADER so + * shift the buffers, skip DOE HEADER in request buffer, and fill DOE + * HEADER in response buffer manually. + */ + + data = le32_to_cpu(*(__le32 *)(request + PCI_DOE_DATA_OBJECT_HEADER_1_OFFSET)); + vendor = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, data); + type = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, data); + + data = le32_to_cpu(*(__le32 *)(request + PCI_DOE_DATA_OBJECT_HEADER_2_OFFSET)); + len = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, data); + + req_pl_sz = len * sizeof(__le32) - PCI_DOE_DATA_OBJECT_HEADER_SIZE; + resp_pl_sz = response_sz - PCI_DOE_DATA_OBJECT_HEADER_SIZE; + req_pl_addr = request + PCI_DOE_DATA_OBJECT_HEADER_SIZE; + resp_pl_addr = response + PCI_DOE_DATA_OBJECT_HEADER_SIZE; + + ret = pci_tsm_doe_transfer(pdev, type, req_pl_addr, req_pl_sz, + resp_pl_addr, resp_pl_sz); + if (ret < 0) { + pci_err(pdev, "spdm msg exchange fail %d\n", ret); + return ret; + } + + data = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, vendor) | + FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, type); + *(__le32 *)(response + PCI_DOE_DATA_OBJECT_HEADER_1_OFFSET) = cpu_to_le32(data); + + len = (ret + PCI_DOE_DATA_OBJECT_HEADER_SIZE) / sizeof(__le32); + data = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, len); + *(__le32 *)(response + PCI_DOE_DATA_OBJECT_HEADER_2_OFFSET) = cpu_to_le32(data); + + ret += PCI_DOE_DATA_OBJECT_HEADER_SIZE; + + pci_dbg(pdev, "%s complete: vendor 0x%x type 0x%x rsp_sz %d\n", + __func__, vendor, type, ret); + return ret; +} + static int tdx_link_connect(struct pci_dev *pdev) { return -ENXIO; -- 2.25.1