From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4BB937DEA0 for ; Tue, 3 Mar 2026 03:16:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772507815; cv=none; b=uq4j2kmgPpOzHgZLolkFnP4iajqbmYiRgYVMZ4ZEzkR80Bcoki7vD/HVXETJ+E+WaHbT63xRYf0Uvv65Y/E6s743zgcbL/RX2gmVyWBzcB/imdU9RXg7Dyr+NqkeFzyuaV69ISlc1MCPl4L8TfwKeZqZHgp2nkoNtYieFz2sFHo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772507815; c=relaxed/simple; bh=gOcQDg6tr6jYCIuV+GW76b897cYlMBwjBDsNGPU73lA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Et6ZyGhaC0ZkV7c42kG2VNIaTbduc0SXnzyQ6wyvn+3eXGcqNWsfq8PxTZb76PHiqLDxhin4GE23L6Gmb20fBQKtsgVB9sSFb+7TJizfrI4BBfUwwN05IKdD0rAopM2DbRk/IJAUQIBMRsiiilwIgg8pQcrmOa85eF2fLVez5yQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WRbtTr/g; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WRbtTr/g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772507813; x=1804043813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gOcQDg6tr6jYCIuV+GW76b897cYlMBwjBDsNGPU73lA=; b=WRbtTr/guMJCM47prcW/i0lgMnYJt/wHAIxjIK3kyGaF6pyZEqXh0U1f zT/8pldrMMDZrB1mQtkZi/UIdPaewuI71S3vOnCsQyrw4ZVFMgRQaeg1Y 0GXr/9Btp2jz3GU6bTH6RXslTQOC6FSw/MEXn9YKwfKS/orHGk1RejLMQ JZEvL63BGYBNhVpcQZSjSLWTWFtxewQbvzTLm17eVzSYpxgxc8JrYMaNV hQ6JIxCi0n5Z33GIfIADTn6FriUYnLJrFhu6PHK8nCTargYs7lemCWmZS Kw6SPTMj+5OVYAoJQbM5lVsRWoFohJP6DzzENR/xyJA1cwb/q0sH2nRBi w==; X-CSE-ConnectionGUID: txL6JozyQ/imZEUq/nkskw== X-CSE-MsgGUID: UwafPPsqTJi9IN0dbPSyUA== X-IronPort-AV: E=McAfee;i="6800,10657,11717"; a="83869743" X-IronPort-AV: E=Sophos;i="6.21,321,1763452800"; d="scan'208";a="83869743" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2026 19:16:53 -0800 X-CSE-ConnectionGUID: eS2Py3QqQDucv00fcLcS6A== X-CSE-MsgGUID: 1nGTwpu5T9GkjJgeoFpxUw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,321,1763452800"; d="scan'208";a="216988919" Received: from lxy-clx-4s.sh.intel.com ([10.239.48.22]) by orviesa006.jf.intel.com with ESMTP; 02 Mar 2026 19:16:50 -0800 From: Xiaoyao Li To: Dave Hansen , Kiryl Shutsemau , Sean Christopherson , Paolo Bonzini Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, Rick Edgecombe , Kai Huang , binbin.wu@linux.intel.com, Tony Lindgren , xiaoyao.li@intel.com Subject: [PATCH v4 3/4] x86/tdx: Rename TDX_ATTR_* to TDX_TD_ATTR_* Date: Tue, 3 Mar 2026 11:03:34 +0800 Message-ID: <20260303030335.766779-4-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260303030335.766779-1-xiaoyao.li@intel.com> References: <20260303030335.766779-1-xiaoyao.li@intel.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The macros TDX_ATTR_* and DEF_TDX_ATTR_* are related to TD attributes, which are TD-scope attributes. Naming them as TDX_ATTR_* can be somewhat confusing and might mislead people into thinking they are TDX global things. Rename TDX_ATTR_* to TDX_TD_ATTR_* to explicitly clarify they are TD-scope things. Suggested-by: Rick Edgecombe Signed-off-by: Xiaoyao Li Reviewed-by: Rick Edgecombe Reviewed-by: Binbin Wu Reviewed-by: Kiryl Shutsemau Acked-by: Sean Christopherson --- arch/x86/coco/tdx/debug.c | 26 ++++++++-------- arch/x86/coco/tdx/tdx.c | 8 ++--- arch/x86/include/asm/shared/tdx.h | 50 +++++++++++++++---------------- arch/x86/kvm/vmx/tdx.c | 4 +-- 4 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/x86/coco/tdx/debug.c b/arch/x86/coco/tdx/debug.c index 28990c2ab0a1..8e477db4ce0a 100644 --- a/arch/x86/coco/tdx/debug.c +++ b/arch/x86/coco/tdx/debug.c @@ -7,21 +7,21 @@ #include #include -#define DEF_TDX_ATTR_NAME(_name) [TDX_ATTR_##_name##_BIT] = __stringify(_name) +#define DEF_TDX_TD_ATTR_NAME(_name) [TDX_TD_ATTR_##_name##_BIT] = __stringify(_name) static __initdata const char *tdx_attributes[] = { - DEF_TDX_ATTR_NAME(DEBUG), - DEF_TDX_ATTR_NAME(HGS_PLUS_PROF), - DEF_TDX_ATTR_NAME(PERF_PROF), - DEF_TDX_ATTR_NAME(PMT_PROF), - DEF_TDX_ATTR_NAME(ICSSD), - DEF_TDX_ATTR_NAME(LASS), - DEF_TDX_ATTR_NAME(SEPT_VE_DISABLE), - DEF_TDX_ATTR_NAME(MIGRATABLE), - DEF_TDX_ATTR_NAME(PKS), - DEF_TDX_ATTR_NAME(KL), - DEF_TDX_ATTR_NAME(TPA), - DEF_TDX_ATTR_NAME(PERFMON), + DEF_TDX_TD_ATTR_NAME(DEBUG), + DEF_TDX_TD_ATTR_NAME(HGS_PLUS_PROF), + DEF_TDX_TD_ATTR_NAME(PERF_PROF), + DEF_TDX_TD_ATTR_NAME(PMT_PROF), + DEF_TDX_TD_ATTR_NAME(ICSSD), + DEF_TDX_TD_ATTR_NAME(LASS), + DEF_TDX_TD_ATTR_NAME(SEPT_VE_DISABLE), + DEF_TDX_TD_ATTR_NAME(MIGRATABLE), + DEF_TDX_TD_ATTR_NAME(PKS), + DEF_TDX_TD_ATTR_NAME(KL), + DEF_TDX_TD_ATTR_NAME(TPA), + DEF_TDX_TD_ATTR_NAME(PERFMON), }; #define DEF_TD_CTLS_NAME(_name) [TD_CTLS_##_name##_BIT] = __stringify(_name) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 7b2833705d47..186915a17c50 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -238,14 +238,14 @@ static void __noreturn tdx_panic(const char *msg) * * TDX 1.0 does not allow the guest to disable SEPT #VE on its own. The VMM * controls if the guest will receive such #VE with TD attribute - * TDX_ATTR_SEPT_VE_DISABLE. + * TDX_TD_ATTR_SEPT_VE_DISABLE. * * Newer TDX modules allow the guest to control if it wants to receive SEPT * violation #VEs. * * Check if the feature is available and disable SEPT #VE if possible. * - * If the TD is allowed to disable/enable SEPT #VEs, the TDX_ATTR_SEPT_VE_DISABLE + * If the TD is allowed to disable/enable SEPT #VEs, the TDX_TD_ATTR_SEPT_VE_DISABLE * attribute is no longer reliable. It reflects the initial state of the * control for the TD, but it will not be updated if someone (e.g. bootloader) * changes it before the kernel starts. Kernel must check TDCS_TD_CTLS bit to @@ -254,14 +254,14 @@ static void __noreturn tdx_panic(const char *msg) static void disable_sept_ve(u64 td_attr) { const char *msg = "TD misconfiguration: SEPT #VE has to be disabled"; - bool debug = td_attr & TDX_ATTR_DEBUG; + bool debug = td_attr & TDX_TD_ATTR_DEBUG; u64 config, controls; /* Is this TD allowed to disable SEPT #VE */ tdg_vm_rd(TDCS_CONFIG_FLAGS, &config); if (!(config & TDCS_CONFIG_FLEXIBLE_PENDING_VE)) { /* No SEPT #VE controls for the guest: check the attribute */ - if (td_attr & TDX_ATTR_SEPT_VE_DISABLE) + if (td_attr & TDX_TD_ATTR_SEPT_VE_DISABLE) return; /* Relax SEPT_VE_DISABLE check for debug TD for backtraces */ diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/shared/tdx.h index 11f3cf30b1ac..049638e3da74 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -20,31 +20,31 @@ #define TDG_VM_RD 7 #define TDG_VM_WR 8 -/* TDX attributes */ -#define TDX_ATTR_DEBUG_BIT 0 -#define TDX_ATTR_DEBUG BIT_ULL(TDX_ATTR_DEBUG_BIT) -#define TDX_ATTR_HGS_PLUS_PROF_BIT 4 -#define TDX_ATTR_HGS_PLUS_PROF BIT_ULL(TDX_ATTR_HGS_PLUS_PROF_BIT) -#define TDX_ATTR_PERF_PROF_BIT 5 -#define TDX_ATTR_PERF_PROF BIT_ULL(TDX_ATTR_PERF_PROF_BIT) -#define TDX_ATTR_PMT_PROF_BIT 6 -#define TDX_ATTR_PMT_PROF BIT_ULL(TDX_ATTR_PMT_PROF_BIT) -#define TDX_ATTR_ICSSD_BIT 16 -#define TDX_ATTR_ICSSD BIT_ULL(TDX_ATTR_ICSSD_BIT) -#define TDX_ATTR_LASS_BIT 27 -#define TDX_ATTR_LASS BIT_ULL(TDX_ATTR_LASS_BIT) -#define TDX_ATTR_SEPT_VE_DISABLE_BIT 28 -#define TDX_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_ATTR_SEPT_VE_DISABLE_BIT) -#define TDX_ATTR_MIGRATABLE_BIT 29 -#define TDX_ATTR_MIGRATABLE BIT_ULL(TDX_ATTR_MIGRATABLE_BIT) -#define TDX_ATTR_PKS_BIT 30 -#define TDX_ATTR_PKS BIT_ULL(TDX_ATTR_PKS_BIT) -#define TDX_ATTR_KL_BIT 31 -#define TDX_ATTR_KL BIT_ULL(TDX_ATTR_KL_BIT) -#define TDX_ATTR_TPA_BIT 62 -#define TDX_ATTR_TPA BIT_ULL(TDX_ATTR_TPA_BIT) -#define TDX_ATTR_PERFMON_BIT 63 -#define TDX_ATTR_PERFMON BIT_ULL(TDX_ATTR_PERFMON_BIT) +/* TDX TD attributes */ +#define TDX_TD_ATTR_DEBUG_BIT 0 +#define TDX_TD_ATTR_DEBUG BIT_ULL(TDX_TD_ATTR_DEBUG_BIT) +#define TDX_TD_ATTR_HGS_PLUS_PROF_BIT 4 +#define TDX_TD_ATTR_HGS_PLUS_PROF BIT_ULL(TDX_TD_ATTR_HGS_PLUS_PROF_BIT) +#define TDX_TD_ATTR_PERF_PROF_BIT 5 +#define TDX_TD_ATTR_PERF_PROF BIT_ULL(TDX_TD_ATTR_PERF_PROF_BIT) +#define TDX_TD_ATTR_PMT_PROF_BIT 6 +#define TDX_TD_ATTR_PMT_PROF BIT_ULL(TDX_TD_ATTR_PMT_PROF_BIT) +#define TDX_TD_ATTR_ICSSD_BIT 16 +#define TDX_TD_ATTR_ICSSD BIT_ULL(TDX_TD_ATTR_ICSSD_BIT) +#define TDX_TD_ATTR_LASS_BIT 27 +#define TDX_TD_ATTR_LASS BIT_ULL(TDX_TD_ATTR_LASS_BIT) +#define TDX_TD_ATTR_SEPT_VE_DISABLE_BIT 28 +#define TDX_TD_ATTR_SEPT_VE_DISABLE BIT_ULL(TDX_TD_ATTR_SEPT_VE_DISABLE_BIT) +#define TDX_TD_ATTR_MIGRATABLE_BIT 29 +#define TDX_TD_ATTR_MIGRATABLE BIT_ULL(TDX_TD_ATTR_MIGRATABLE_BIT) +#define TDX_TD_ATTR_PKS_BIT 30 +#define TDX_TD_ATTR_PKS BIT_ULL(TDX_TD_ATTR_PKS_BIT) +#define TDX_TD_ATTR_KL_BIT 31 +#define TDX_TD_ATTR_KL BIT_ULL(TDX_TD_ATTR_KL_BIT) +#define TDX_TD_ATTR_TPA_BIT 62 +#define TDX_TD_ATTR_TPA BIT_ULL(TDX_TD_ATTR_TPA_BIT) +#define TDX_TD_ATTR_PERFMON_BIT 63 +#define TDX_TD_ATTR_PERFMON BIT_ULL(TDX_TD_ATTR_PERFMON_BIT) /* TDX TD-Scope Metadata. To be used by TDG.VM.WR and TDG.VM.RD */ #define TDCS_CONFIG_FLAGS 0x1110000300000016 diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index f38e492fb3d5..c5065f84b78b 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -75,7 +75,7 @@ void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass, char *op, u32 field, pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, val, err); } -#define KVM_SUPPORTED_TD_ATTRS (TDX_ATTR_SEPT_VE_DISABLE) +#define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE) static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm) { @@ -707,7 +707,7 @@ int tdx_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.l1_tsc_scaling_ratio = kvm_tdx->tsc_multiplier; vcpu->arch.guest_state_protected = - !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_ATTR_DEBUG); + !(to_kvm_tdx(vcpu->kvm)->attributes & TDX_TD_ATTR_DEBUG); if ((kvm_tdx->xfam & XFEATURE_MASK_XTILE) == XFEATURE_MASK_XTILE) vcpu->arch.xfd_no_write_intercept = true; -- 2.43.0