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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5075feb4db9sm79588961cf.22.2026.03.03.04.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 04:15:09 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vxOea-00000004CWJ-1Uzg; Tue, 03 Mar 2026 08:15:08 -0400 Date: Tue, 3 Mar 2026 08:15:08 -0400 From: Jason Gunthorpe To: Alexey Kardashevskiy Cc: Robin Murphy , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-pci@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Andy Lutomirski , Peter Zijlstra , Bjorn Helgaas , Dan Williams , Marek Szyprowski , Andrew Morton , Catalin Marinas , Michael Ellerman , Mike Rapoport , Tom Lendacky , Ard Biesheuvel , Ashish Kalra , Stefano Garzarella , Melody Wang , Seongman Lee , Joerg Roedel , Nikunj A Dadhania , Michael Roth , Suravee Suthikulpanit , Andi Kleen , Kuppuswamy Sathyanarayanan , Tony Luck , David Woodhouse , Greg Kroah-Hartman , Denis Efremov , Geliang Tang , Piotr Gregor , "Michael S. Tsirkin" , Alex Williamson , Arnd Bergmann , Jesse Barnes , Jacob Pan , Yinghai Lu , Kevin Brodsky , Jonathan Cameron , "Aneesh Kumar K.V (Arm)" , Xu Yilun , Herbert Xu , Kim Phillips , Konrad Rzeszutek Wilk , Stefano Stabellini , Claire Chang , linux-coco@lists.linux.dev, iommu@lists.linux.dev, Jiri Pirko Subject: Re: [PATCH kernel 6/9] x86/dma-direct: Stop changing encrypted page state for TDISP devices Message-ID: <20260303121508.GD964116@ziepe.ca> References: <20260225053806.3311234-1-aik@amd.com> <20260225053806.3311234-7-aik@amd.com> <20260228000630.GN44359@ziepe.ca> <2a5b2d8c-7359-42bd-9e8e-2c3efacee747@amd.com> <20260302003535.GU44359@ziepe.ca> <500e3174-9aa1-464a-b933-f0bcc2ddde68@amd.com> <20260302133527.GV44359@ziepe.ca> <9cf2e2e6-0fe2-4804-9c62-bc60c89d57c1@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9cf2e2e6-0fe2-4804-9c62-bc60c89d57c1@amd.com> On Tue, Mar 03, 2026 at 07:19:36PM +1100, Alexey Kardashevskiy wrote: > > It seems from your email that the CPU S2 has the Cbit as part of the > > address and the S1 feeds it through to the S2, so it is genuinely has > > two addres spaces? > > S1/S2 PTEs have Cbit. Addresses to look up those PTEs - do not. So we are back to what I was saying before: using phys_addr_t to encode a PTE bit is probably a very confusing idea - especially when contrasted with the other arches that have a legitimate address bit. > > Same way it knows if there is no S1? > > If no S1 - then sDTE decides on Cbit for the entire ASID (with the help of vTOM). Sounds like the intention was the IOMMU shared/private space would be controlled with vTOM which actually does a create a legitimate address bit in the phys_addr_t. A sDTE global control is OK for non-TDISP devices, or even devices that haven't entered RUN yet, but it is not OK for a TDISP device that must still be able to access shared memory. > I understand I am often confusing, trying to unconfuse (including myself)... Thanks, It seems to me the AMD architecture itself is pretty confusing. :\ Jason