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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YIxwTvjOGzyDtQ/qPTjl31qYQh5OfcYQhoUbUVLYyRaHcsg3M5idWH0Q1zJvb2peb7khEKh0lzWIk9XQmxZRhICLscEaz0/ETPXXXNSWdBAT4ALH/6CdF2HNBKfVrD9v/oYCKdQF1vJmL4D8epIfEZBgS6e6E0xQTxR4BQCBieAh2KjJ8qftHARYBBiagWXdot+aoKHmP4HpDuYaqzHnX+vI5HCO9wne/ozqyPesh7tcIJF20YF7vrv8kL8wFXdDFzOFABleFEoY9GvnvGSV4beZdN8KwRYYNmGfmDNVp6hczov4Vc7uJPLozioXCuudGLRi5UmDeJbfMLBreEzLMSJQ/BEP2yqcbIeerxaOeQx3MILIwuzkj7tvjZCKzC5XvPxmC7RLdNoI3WSaHF9E7iW2GA18OpBY4ebiqgFa2zqtf6bEDGC6/z9D5pJL/MJ+ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2026 13:06:22.8011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b19bd280-3181-4772-f824-08de7f6efea2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6606 This feature ensures SNP guest Branch Target Buffers (BTBs) are not affected by context outside that guest. The first patch fixes a longstanding bug where users weren't able to force Automatic IBRS on SNP enabled machines using spectre_v2=eibrs. The second patch fixes another longstanding bug where users couldn't select legacy / toggling SPEC_CTRL[IBRS] on AMD systems. Users of the BTB Isolation feature may use IBRS to mitigate possible performance degradation caused by BTB Isolation. The third patch adds support for the feature by adding it to the supported features bitmask. Based on tip/master, currently 7726ce228780. https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git This series also available here: https://github.com/AMDESE/linux/tree/btb-isol-latest Advance qemu bits (to add btb-isol=on/off switch) available here: https://github.com/AMDESE/qemu/tree/btb-isol-latest Qemu bits will be posted upstream once kernel bits are merged. They depend on Naveen Rao's "target/i386: SEV: Add support for enabling VMSA SEV features": https://lore.kernel.org/qemu-devel/cover.1761648149.git.naveen@kernel.org/ v2: - Patch 1/3: - Address Dave Hansen's comment to adhere to using the IBRS_ENHANCED Intel feature flag also for AutoIBRS. v1: https://lore.kernel.org/kvm/20260224180157.725159-1-kim.phillips@amd.com/ Kim Phillips (3): cpu/bugs: Allow forcing Automatic IBRS with SNP enabled using spectre_v2=eibrs cpu/bugs: Allow spectre_v2=ibrs on x86 vendors other than Intel KVM: SEV: Add support for SNP BTB Isolation arch/x86/include/asm/svm.h | 1 + arch/x86/kernel/cpu/bugs.c | 19 +++++++++++-------- arch/x86/kernel/cpu/common.c | 6 +----- arch/x86/kvm/svm/sev.c | 3 +++ 4 files changed, 16 insertions(+), 13 deletions(-) base-commit: 7726ce2287804e70b2bf2fc00f104530b603d3f3 -- 2.43.0