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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?lqrqDy9EzTZXxYD2RIGsUKFpbVmU6/W+DTQiVj8pYnf0nAnzsiJt5Hu4RwvH?= =?us-ascii?Q?3sWvjvcuvch6qVc0m9v6K84TFX4ixUgMaHbPr4GXf/kLNcI1AH+bZL624OxO?= =?us-ascii?Q?kYWcTHqz5LgsoRTZEKcagoHfRbsZx5hQqK+YSFd3/GGgiYphiY71tCFjnJ8w?= =?us-ascii?Q?e3V/gbPGGB+vt04eI2CFkdozf9jonO8uU8CYGkWaYC6wyHR+maAkddU4CrmA?= =?us-ascii?Q?YwUN/nJrWpL4nY+bfXOj1iEeP2N/kEx6Ft2xbJpYvhuc3tOyO6rRZ5DI193N?= =?us-ascii?Q?0YfFkCfOn7ttImJawiNm6nc8AKBOdOJKLbGZl/PHnE58Dq/7pPYS9WH/FbvV?= =?us-ascii?Q?i6z//1NSU48JuSTL8LYpNAjV4fTAd7y5YylTht8IHTftLr0OV3BXZn9D/ZRV?= =?us-ascii?Q?AMEtCzMoGOv4PRXx0b89280/R1+SYktqrc50YifncqY/ult07Nb37lqf9fG0?= =?us-ascii?Q?O/VyAVf+uUS/bzh2HND+hFjqz9KF2gSGYd+FIMD0zepF1sEldJAXGqHbaRD7?= =?us-ascii?Q?cTXNV2QegWsYmHN5Gj9ISl/X2QUI9gsJ07oZYEJRWKxCN7VKJ7A/QjU8WyI5?= =?us-ascii?Q?M5GB70+VVNACRaQG0NdVZm3pRrNqTTV73qTCDPR3Wnrm+u9fEkWmXS8svKVw?= =?us-ascii?Q?5RdGqpyKdqOk/NVcPsYxqH44XphQaSaMbM17vo+GJZ+gbLM7gi994UBFvcz8?= =?us-ascii?Q?ouaymjcFxyJx60KiEtaNh8Od6QEGw5kIumzcfpaE2hVY3klALK5vR8WDhkeO?= =?us-ascii?Q?Rquo89/KUX9qB+kCRP34aZkSv+caMceHwt0QJUY/Ta0/6E2SutviqG3k/ro1?= =?us-ascii?Q?ZW9m873bma3adTfp9HF5zAphYApNXDkEMYEW8ABNgatHtz6Qs5BQqsIR15ZF?= =?us-ascii?Q?2hE7KISSlOs3S6sPmbfyyTzeqUH4i3oKOa/5N2cpLI27ew1jlaaa1dlHsb/o?= =?us-ascii?Q?1GlAXf6E1U1rndSkUFn64+YHsE5ln0C3FdRBnDBYl7M6k8S6wQ6jzOOrQVqw?= =?us-ascii?Q?Yc8W3qAfTkjGeU+6gQEbt/70kKhiRz2xbxEvyIRnNCpUJm1I3sit6auAGlfx?= =?us-ascii?Q?nl+XHH0i6Pr7dS2c4k6sEiIIkgJNXU+Frh4Q/zcStkSuI1cpwVFkhKzXoLl5?= =?us-ascii?Q?jtA+/5ohP/m/ihUoCfTEH8Xq8ySQecdjWHB5kXTVmCq6eFaOI7QtNBNShvmn?= =?us-ascii?Q?5rDdXnVG3KHUb2VV2c1CP/HnT4CvRoVG4qstG9AA9x5pquUP0gQ3Xu69p3Hk?= =?us-ascii?Q?NdDQeNuPdFNHogS3CK80rwrwbU9rc0zkPAGdqwQs4MR+xMFZtjjnGgKUotS3?= =?us-ascii?Q?Ul35UlhT4yCJGWgHhyIl9JYIAtfxBu0RF1BrJ/AddQAaj06gHLaqjqRAVFUS?= =?us-ascii?Q?0gXYGRXZvOt1wCTP3onV2Xo1uuPNDT451iSZFLBoz1Xm17nJorT5mlPEM4S8?= =?us-ascii?Q?CkkK5FZY1CfGd7/++6AOx37PWC3G4cxcOeawKU/vLG/c4yEYdDXjYjTARi4g?= =?us-ascii?Q?9EItnLLWWGQyGpX/Nx9KZB6i9oFOLhr02yWQLxBt85ROSLaSGh6oy9gTNJLN?= =?us-ascii?Q?AdDIi36yH9vF6AZhx+gar0H+wYYyLdj9tMZIPug43YJX2NiWyZ38VGLe/10Q?= =?us-ascii?Q?JFBvr1H0ocFSOGwIneJwZsP9YnCEkGtDJM6XIDjFywAX8UzBZQSO7wevBD3l?= =?us-ascii?Q?RZcO9zOSH+6zkaV9faI1nlkLjJ3cCj3IA0qYC0+tdzEAklzl?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 132e5ecd-d845-42e1-7c69-08de958f8e80 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 16:54:53.8978 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bz3rEKyG3F+y/9xcFun6fKddVDBnEFvTnbI5d7SzTrIcYWU0Vxtv90uOuXVqsS+H X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7358 On Wed, Apr 08, 2026 at 05:03:16PM +1000, Alexey Kardashevskiy wrote: > > > This is what I am trying to clarify - if all ranges muI thinkst be reported > > > (as some think this is what the PCIe spec says), then no, not > > > anywhere. > > > > > > pcie r7, Table 11-16 TDI Report Structure, MMIO_RANGE: > > > > > > "Each MMIO Range of the TDI is reported with the MMIO reporting offset added." > > > > I think the argument was something like it didn't have to report > > non-secure ranges? But I don't know, it was hashed out in some thread > > for ARM and then I know our folks looked at it and nobody pushed back > > to insist that every single byte of the BAR had to be covered by a > > reported range. > > That's (my ignorant guess) because of the ARM FW TSM guy which sees the BARs and can easily make sure that MMIO_OFFSET is such that BAR alignment is preserved (and there is a clause in PCIe about how such offset is "permitted" to be calculated) => does not make much difference on ARM but it does in my case :-/ > > I wouldn't take the sentance you quoted as confirmation, you need a > > sentance that says every single byte of the BAR is covered by a single > > reported range. > > Why "by a single range"? Every byte of a BAR needs to be covered > (which is what my quote suggests) No, your quote doesn't suggest that at all, it just says if a range is present it has to be offset. In fact the spec specifically says not to report ranges sometimes: Bit 0 - MSI-X Table - if the range maps MSI-X table. This must be reported **only if locked** by the LOCK_INTERFACE_REQUEST. So if the MSI-X table is not locked then what is reported? Seems not covered by a range at all is the consensus answer. Thus you get this case where the non-reported MSI-X table could be at byte 0, not get a range and then there is no range covering byte 0 of the bar at all. > and the spec allows multiple ranges but also requires strict > ascending order of the ranges, 3 paragraphs of text about > it. Thanks, single range per byte means there are not overlapping ranges. This was the old thread with my suggestion. https://lore.kernel.org/all/20250911134107.GG882933@ziepe.ca/ If this is important to AMD they need to get an ECN with PCI-SIG to clarify. I think as of right now Linux can't assume the ranges start at bar physical offset 0. Jason