From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AEA9345BD4E; Wed, 13 May 2026 13:20:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778678412; cv=none; b=WNCzc4Y2irTTpAwN1Xk4cKQWzjwt965Gmof0/ByROlDK2DDMO04/kKe74GP0jEDdoLdxwt2JI7nDPV3t93VCF/xGmkzKR9X+AG68a/FKWBGAhBj0UJMBFhjBVteC6R2gDGPfdSNtWnA59M7sy4eYf79mr8FXbs+GJuIDuaaIa0U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778678412; c=relaxed/simple; bh=ZB3UfWMBWi47xNi/1RiPQdmJAQA9R3+zNe+L9EeKetg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sbaAeg1ZQdSfHYN1boWsMdI14eSibj+ekfRDTPEJ5zIgJcO5UbwOCWz8wD4v7Xi1x24ppZRbZIx2QtXPU7XUrdfvpjPNdQ1y7uUf350L8VDEBY+d7f63zKK0PS3pr9cfFUwUwWeUoB0vcOY0NDNYTdwkd2osuvQirHtYtjHNROo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Ihtg60wk; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Ihtg60wk" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E7898302D; Wed, 13 May 2026 06:20:04 -0700 (PDT) Received: from e122027.arm.com (unknown [10.57.68.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2B9A53F836; Wed, 13 May 2026 06:20:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778678410; bh=ZB3UfWMBWi47xNi/1RiPQdmJAQA9R3+zNe+L9EeKetg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ihtg60wkBVhkbym7aHRRU6cleylvpw4kTszAjZn54Mu+LbyY0M8VfQQblBDQYpJnr IrTjWbTZ8kOPVsm9hPm1/PQf5afjpYd8ppUfs6zVdIBopFEIHTP6PaKLgzuWtaGZHY 8tTo5656YbFNXFFNHfDEQDaORPWw1PgLNpZD2Ess= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo.Pieralisi2@arm.com Subject: [PATCH v14 20/44] arm64: RMI: Support for the VGIC in realms Date: Wed, 13 May 2026 14:17:28 +0100 Message-ID: <20260513131757.116630-21-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260513131757.116630-1-steven.price@arm.com> References: <20260513131757.116630-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RMM provides emulation of a VGIC to the realm guest. With RMM v2.0 the registers are passed in the system registers so this works similar to a normal guest, but kvm_arch_vcpu_put() need reordering to early out, and realm guests don't support GICv2 even if the host does. Signed-off-by: Steven Price --- Changes from v12: * GIC registers are now passed in the system registers rather than via rec_entry/rec_exit which removes most of the changes. Changes from v11: * Minor changes to align with the previous patches. Note that the VGIC handling will change with RMM v2.0. Changes from v10: * Make sure we sync the VGIC v4 state, and only populate valid lrs from the list. Changes from v9: * Copy gicv3_vmcr from the RMM at the same time as gicv3_hcr rather than having to handle that as a special case. Changes from v8: * Propagate gicv3_hcr to from the RMM. Changes from v5: * Handle RMM providing fewer GIC LRs than the hardware supports. --- arch/arm64/kvm/arm.c | 11 ++++++++--- arch/arm64/kvm/vgic/vgic-init.c | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 93d34762db91..21d9dfdb1ea0 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -786,19 +786,24 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_call_hyp_nvhe(__pkvm_vcpu_put); } + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); + + vcpu->cpu = -1; + + if (vcpu_is_rec(vcpu)) + return; + kvm_vcpu_put_debug(vcpu); kvm_arch_vcpu_put_fp(vcpu); if (has_vhe()) kvm_vcpu_put_vhe(vcpu); - kvm_timer_vcpu_put(vcpu); - kvm_vgic_put(vcpu); kvm_vcpu_pmu_restore_host(vcpu); if (vcpu_has_nv(vcpu)) kvm_vcpu_put_hw_mmu(vcpu); kvm_arm_vmid_clear_active(); vcpu_clear_on_unsupported_cpu(vcpu); - vcpu->cpu = -1; } static void __kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 933983bb2005..a9db963dfd23 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -81,7 +81,7 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) * the proper checks already. */ if (type == KVM_DEV_TYPE_ARM_VGIC_V2 && - !kvm_vgic_global_state.can_emulate_gicv2) + (!kvm_vgic_global_state.can_emulate_gicv2 || kvm_is_realm(kvm))) return -ENODEV; /* -- 2.43.0