From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C97AC412275 for ; Wed, 1 Jul 2026 19:32:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782934378; cv=none; b=b6DFChioV6RDoCFTn8JrC7/CTgu9/rlvaNnsuQOKL7zDm6E1hFYdUs3gxceZtInWU0oiPDZb/H7g8Ea75m6TY3EITH42Wk4ZFaNAPT0P6zuzxGfZZBNuRkSgcuwdMLMLFWy5ChzyJRjOzoqW9wgYgKV59iVwFBRUUIftsTVvmZI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782934378; c=relaxed/simple; bh=ehvol4aPGGdBph7tPEcdqNiMmKvh5DD8WD/ckSXpqow=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=TdXbXpKxmPQlhZm38xCZEZ5xuR6YhkRM4Aa/okbEq5sw5nVJlHqfOugg3mndOmgyqXRTyrVZxPUxgKCNIezD3JGBpZDtK16xk09KWMpVYyfT46x5X8wPioYzjv+pFRn+vio0rK9Jf7vQko+NqfO9icDrAP3MBfZncK40i5eWQVM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=lgneI6us; arc=none smtp.client-ip=209.85.214.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="lgneI6us" Received: by mail-pl1-f201.google.com with SMTP id d9443c01a7336-2c9b1b608e2so14564575ad.3 for ; Wed, 01 Jul 2026 12:32:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1782934375; x=1783539175; darn=lists.linux.dev; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=XQAPpCEE/BDkXN3dIWP18HQMEopEl3zLKZ2PUcc2V5o=; b=lgneI6usjDsLdcadq7LQV/mWyWl6q5gdPRt40NdWku6zwORBvFxRxrFzCrWnk7pClf YsIoFvTNZJ9N0OL2if9lwxJoeJUW0BG12lzID9LIvrvmVDzDYbGQcd7hQYHxM3xczY8X F5ITaeMDIrXsLjfgPwlA2mEENQVqHfIN/j+eKnts/Pq6A37K5s7bjvi6naB6wD/JA5uG n5rHHrNrP20L0EzSIV39edh3GtGjeVYVdGw9IeP+5DWCpAGu7doHxATXGyGDIHcpUWmo /iprkHEOPFFhwsgKVvS7a/tQpoiYmmTB1/Lvqas/iUxPmyksnFO6/Q3oB34hXxzjkDF/ HQ1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782934375; x=1783539175; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=XQAPpCEE/BDkXN3dIWP18HQMEopEl3zLKZ2PUcc2V5o=; b=b9/iYeYyZxEgua1Ah5WgsMKh8RUrGYtZmnnQjwZu9zVcJB+9mDCaX0w9Z3gGf6yolB jc5XIdLS7y5CkSrkK1BjbiLrRj3d7FYOGIZZJ7SdfEZ84TWP1bxVCAuFhUoRtERTHNqb WgsFEeLjA8EG6tnEOAjomEngoRQ8uw/IEsVYvzPUxF1neIUnxeJuKzhIUQvoeC7aAORU kPs7TWzwhferj4pitUqyX08R918nZyy6nbTVVT1Pf8yTYDSNtYcbDege9cD/BRrxh+4V h5ermYR570Xh308563xA/OXKtokwg/OYSP7mPsh5AcP94LSBX+h+y7F+TtSaVPxuFsCX eC8Q== X-Forwarded-Encrypted: i=1; AHgh+RqLQX68eQXAmj6QIG6c6DZmHw0wpaa0GYupmAYStrrAFE3XIuE4eK1nym3lf0WVyMUGADOD27skBSVo@lists.linux.dev X-Gm-Message-State: AOJu0YwgwQbYAJpzO8bqXOnRcGe9vcpwmQVT2boW2e0jBVCExto8tYh/ /esg80nzPOKs8Rx0wUms3S1sKCJAz0QKXFtPpvKSWS/LHu6GePJtfXhu5AHMqhf2ezzbVxCakMU jasT7Aw== X-Received: from plpl11.prod.google.com ([2002:a17:903:3dcb:b0:2b0:46bd:4fe5]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:ce02:b0:2ca:62e:cc4f with SMTP id d9443c01a7336-2ca7e7645d1mr34535395ad.23.1782934374801; Wed, 01 Jul 2026 12:32:54 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 1 Jul 2026 12:31:44 -0700 In-Reply-To: <20260701193212.749551-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260701193212.749551-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.rc0.799.gd6f94ed593-goog Message-ID: <20260701193212.749551-24-seanjc@google.com> Subject: [PATCH v5 23/51] x86/tsc: Add standalone helper for getting CPU frequency from CPUID From: Sean Christopherson To: Jonathan Corbet , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Ajay Kaher , Alexey Makhalov , Jan Kiszka , Andy Lutomirski , Peter Zijlstra , Juergen Gross , Daniel Lezcano , John Stultz Cc: Shuah Khan , "H. Peter Anvin" , Vitaly Kuznetsov , Broadcom internal kernel review list , Boris Ostrovsky , Stephen Boyd , linux-doc@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, xen-devel@lists.xenproject.org, Tom Lendacky , Nikunj A Dadhania , David Woodhouse , David Woodhouse , Michael Kelley , Thomas Gleixner Content-Type: text/plain; charset="UTF-8" Extract the guts of cpu_khz_from_cpuid() to a standalone helper that doesn't restrict the usage to Intel CPUs. This will allow sharing the core logic with KVM-as-a-guest, as KVM generally doesn't restrict CPUID based on vendor. No functional change intended. Reviewed-by: David Woodhouse Signed-off-by: Sean Christopherson --- arch/x86/include/asm/tsc.h | 1 + arch/x86/kernel/tsc.c | 31 +++++++++++++++---------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index c09ec485abcd..cb682f097ea7 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -88,6 +88,7 @@ struct cpuid_tsc_info { unsigned int crystal_khz; }; extern int cpuid_get_tsc_info(struct cpuid_tsc_info *info); +extern unsigned int __cpu_khz_from_cpuid(void); extern void tsc_early_init(void); extern void tsc_init(void); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 6ed6f8f012eb..56e73e96920a 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -668,6 +668,18 @@ int cpuid_get_tsc_info(struct cpuid_tsc_info *info) return 0; } +unsigned int __cpu_khz_from_cpuid(void) +{ + unsigned int eax_base_mhz, ebx, ecx, edx; + + if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ) + return 0; + + cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); + + return eax_base_mhz * 1000; +} + /** * native_calibrate_tsc - determine TSC frequency * Determine TSC frequency via CPUID, else return 0. @@ -703,12 +715,8 @@ static unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (!info.crystal_khz && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) { - unsigned int eax_base_mhz, ebx, ecx, edx; - - cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); - info.crystal_khz = eax_base_mhz * 1000 * info.denominator / info.numerator; - } + if (!info.crystal_khz) + info.crystal_khz = __cpu_khz_from_cpuid() * info.denominator / info.numerator; if (!info.crystal_khz) return 0; @@ -733,19 +741,10 @@ static unsigned long native_calibrate_tsc(void) static unsigned long cpu_khz_from_cpuid(void) { - unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return 0; - if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ) - return 0; - - eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; - - cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); - - return eax_base_mhz * 1000; + return __cpu_khz_from_cpuid(); } /* -- 2.55.0.rc0.799.gd6f94ed593-goog