From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1ABC8388395; Wed, 15 Jul 2026 14:29:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125801; cv=none; b=EDGOlWKMbRMRJ3aXsg4csZAPevd5nb3vlt+r1feUAjABQK5ZfoKraPOmOdspqxcQcBs9rDTn9fO09nuj+rFHaWlz/+gtGSAc8HSbxRCfWQEdqg/lv7MRru4VVY4ruu3QmuNXIYdMGl2tMzH7EKlpxR0xLNMvhPNbafraCV+tjeY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125801; c=relaxed/simple; bh=ALLLCbjfHABpvO+YbrVszcEBpAomTIT3qE5M78Zf9q0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sSpD+UiKb85D0A6sN2fY22W/YtJelj6cA56LHXdNZiXwXHqdXljj9LBad55QJpen96gtNuYNTUI7cEaC2ANk5vo0xmJ3qz7jNJV+ZBGYX1EAIFLZkjCQvFGS7bZUZPtmNnFlN6qipqFctDuZgyuWlFemWwoKVLuIOk+hSfaW5sk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=iFCnmRDM; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="iFCnmRDM" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2852F153B; Wed, 15 Jul 2026 07:29:53 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0D5F3F7B4; Wed, 15 Jul 2026 07:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125797; bh=ALLLCbjfHABpvO+YbrVszcEBpAomTIT3qE5M78Zf9q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iFCnmRDM0jeVC9Yrqx/QO2Lz8C+Ex5cCZgAmxrJenWt9ZOD2mBhtpSoY8uaPYujWl N3WAtbiWFZhtSXtbjuaveZc2iratk7L+Xu581qWJxz6JihSbBMGelwsGOh6+d51DS6 eUDm3mBrJD9xeLEN6e0s1lCzPpJhvS2UyJFiCREM= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 13/37] KVM: arm64: CCA: Support timers in realm RECs Date: Wed, 15 Jul 2026 15:28:15 +0100 Message-ID: <20260715142841.80544-14-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RMM keeps track of the timer while the realm REC is running, but on exit to the normal world KVM is responsible for handling the timers. A later patch adds the support for propagating the timer values from the exit data structure and calling kvm_realm_timers_update(). Signed-off-by: Steven Price --- Changes since v14: * Special case in kvm_timer_vcpu_load()/kvm_timer_vcpu_put() the timer handling. Changes since v12: * Adapt to upstream changes. Changes since v11: * Drop the kvm_is_realm() check from timer_set_offset(). We already ensure that the offset is 0 when calling the function. Changes since v10: * KVM_CAP_COUNTER_OFFSET is now already hidden by a previous patch. Changes since v9: * No need to move the call to kvm_timer_unblocking() in kvm_timer_vcpu_load(). Changes since v7: * Hide KVM_CAP_COUNTER_OFFSET for realm guests. --- arch/arm64/kvm/arch_timer.c | 38 +++++++++++++++++++++++++++++++++--- include/kvm/arm_arch_timer.h | 2 ++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 4155fe89b58a..fdd68f1f5b7b 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -482,6 +482,20 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level, timer_ctx); } +void kvm_realm_timers_update(struct kvm_vcpu *vcpu) +{ + struct arch_timer_cpu *arch_timer = &vcpu->arch.timer_cpu; + int i; + + for (i = 0; i < NR_KVM_EL0_TIMERS; i++) { + struct arch_timer_context *timer = &arch_timer->timers[i]; + bool status = timer_get_ctl(timer) & ARCH_TIMER_CTRL_IT_STAT; + bool level = kvm_timer_enabled(timer) && status; + + kvm_timer_update_irq(vcpu, level, timer); + } +} + /* Only called for a fully emulated timer */ static void timer_emulate(struct arch_timer_context *ctx) { @@ -888,6 +902,11 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; + if (vcpu_is_rec(vcpu)) { + kvm_timer_unblocking(vcpu); + return; + } + get_timer_map(vcpu, &map); if (static_branch_likely(&has_gic_active_state)) { @@ -923,6 +942,12 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; + if (vcpu_is_rec(vcpu)) { + if (kvm_vcpu_is_blocking(vcpu)) + kvm_timer_blocking(vcpu); + return; + } + get_timer_map(vcpu, &map); timer_save_state(map.direct_vtimer); @@ -1073,7 +1098,7 @@ static void timer_context_init(struct kvm_vcpu *vcpu, int timerid) ctxt->timer_id = timerid; - if (!kvm_vm_is_protected(vcpu->kvm)) { + if (!kvm_vm_is_protected(vcpu->kvm) && !vcpu_is_rec(vcpu)) { if (timerid == TIMER_VTIMER) ctxt->offset.vm_offset = &kvm->arch.timer_data.voffset; else @@ -1104,7 +1129,7 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) timer_context_init(vcpu, i); /* Synchronize offsets across timers of a VM if not already provided */ - if (!vcpu_is_protected(vcpu) && + if (!vcpu_is_protected(vcpu) && !vcpu_is_rec(vcpu) && !test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read()); timer_set_offset(vcpu_ptimer(vcpu), 0); @@ -1600,6 +1625,13 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) return -EINVAL; } + /* + * We don't use mapped IRQs for Realms because the RMI doesn't allow + * us setting the LR.HW bit in the VGIC. + */ + if (vcpu_is_rec(vcpu)) + return 0; + get_timer_map(vcpu, &map); ops = vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : @@ -1729,7 +1761,7 @@ int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, if (offset->reserved) return -EINVAL; - if (kvm_vm_is_protected(kvm)) + if (kvm_vm_is_protected(kvm) || kvm_is_realm(kvm)) return -EINVAL; mutex_lock(&kvm->lock); diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 15a4f97f8105..31e48d5dbc31 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -108,6 +108,8 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); int kvm_arm_timer_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); +void kvm_realm_timers_update(struct kvm_vcpu *vcpu); + u64 kvm_phys_timer_read(void); void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu); -- 2.43.0