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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SA2PEPF000015C9.mail.protection.outlook.com (10.167.241.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.360.3 via Frontend Transport; Fri, 21 Aug 2026 05:58:23 +0000 Received: from BLR-L1-SARUNKOD.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Fri, 21 Aug 2026 00:58:15 -0500 From: Sairaj Kodilkar To: "Borislav Petkov (AMD)" , "H. Peter Anvin" , "Joerg Roedel (AMD)" , "Paul E. McKenney" , Andrew Morton , Breno Leitao , Christian Brauner , Dapeng Mi , Dave Hansen , "Eric Biggers" , Ingo Molnar , Jakub Kicinski , Jonathan Corbet , Kiryl Shutsemau , Li RongQing , Marco Elver , Paolo Bonzini , Rick Edgecombe , Robin Murphy , "Sairaj Kodilkar" , Sean Christopherson , "Shuah Khan" , Suravee Suthikulpanit , Thomas Gleixner , "Vasant Hegde" , Will Deacon , , , , , , Subject: [PATCH v4 4/7] iommu/amd: Program guest-mode IRTEs for GAPPI wakeup when IRTE[IsRun] = 0 Date: Fri, 21 Aug 2026 11:26:08 +0530 Message-ID: <20260821055611.27138-5-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260821055611.27138-1-sarunkod@amd.com> References: <20260821055611.27138-1-sarunkod@amd.com> Precedence: bulk X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C9:EE_|IA1PR12MB6091:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a7ec9b3-3b6d-4dff-74fe-08deff49362d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|23010399003|82310400026|36860700016|22082099003|18002099003|56012099006|13003099007|11063799006|10067099003|921020; X-Microsoft-Antispam-Message-Info: mjEZYLFSwpfOoN/+FqF2AqWT10/RTYH69SICPYOs4/MGtjhGtzZxRMvMw/diYoYpl+tUOnjq6WEUR1zbFKu5MNgMy/a9SfddZydWbkD5i3xIlq9M2U57pLdymu0ih4tpuOucNNET/6E3MVIRBrGsJIjqgT5UkIT24IUseN+qjwHbtpT91IUyVBPn6iDkSyW03qKtYFQuTkQb6zVVtCMVBoheK/lU5koGTCmwY1H+/W47BzmLxKtbJQZM8uQ2J0cP/uit/yE6OGz+OKoOEXEFY8NrHe94fk8idYYH28t4BQkZjC24GTEmO+G5C7kgDGtemT1rA9fnzFLd8brBcsUgAoDtcTunq8/h/fzPSsH5WwauMzdiTGUUbksg6GTbGsP2cuVe5BK2WmOqRdJmtfSDZ09gONXQ+hJii6Era1fH/+k4Y1HjOohEJUD8VHQxDJOBKq9rfB34PwlFb/9xXHnSidgy3P7vNgALCtmsfy1kFjgHZbOUhSr3DhdL9xypwcoGwJFhXCVJGXNUHV20iqKk6qhe91U47S3jgn7kPHpe8F7cJMao0E4Fr+w/1ELif2p+JjPOPbY9FmTQ1JVicoiE56UvQXCyNMxCteHWcEp823ZGUy9qWcM+hoQwQzZ7shJhVNfz+xVuJWxGI3Hth+EWIeRA1Hy3/bf/glsD1IBDesJK7KBBJJt69qK266zmdmDRBQqr4gXOQl1H7T4M861qWZsCN0YN7EhWoHJZl9N3lpYgrbjf1qi7yC2KLlEo88zf X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(23010399003)(82310400026)(36860700016)(22082099003)(18002099003)(56012099006)(13003099007)(11063799006)(10067099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LRLc7ZybUwP63EVmjo4H6aoKbuTwJ5qwY6jsDp/VSwhIs4OCi1JEMA5qU5EOmSjzrvLaUX6TzxpLDWHGmfxFmaUlSOGMOrl7eZNY74s3o0nGwv4QNoKl9FqfK5+6GaBwY6UXJ5pG4DfWSEVFcLU4n1aJAK2rzc9JRmPVefTU4mwMlG6srRtba4C94SWh8fQCDhHH43Mp2M6X6nO+5h4totH0C9xf5nj8E6zLVKduLkF8vGlzfwGPP0/elqPUgl1Nn0+k5nF0I7PNhX7mbzbtw8qGAqCoPzB2+6HQlwwKsBsa6rxIojh1synMG6CgBe5lqWOKPYdJuSt0+oHxXArB/2bxfE7seG/2KO0ZMvbZ3GJd3FSk4LFxgBbL4eAjUTB7pDx6A3NT28KIDb8qCl8ITMPhg8TaR6cDWNZ/dT+WgQBlooDv6NZpGawiHd2ouben X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2026 05:58:23.9195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a7ec9b3-3b6d-4dff-74fe-08deff49362d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6091 Guest APIC Physical Processor Interrupt (GAPPI) is an alternative to the GA log for notifying the host when a device interrupt targets a non-running vCPU (IRTE[IsRun] = 0). Per the AMD IOMMU specification [1] (section 2.2.5.4), with GAPPI enabled the IOMMU delivers a physical APIC interrupt to the CPU described by IRTE[Destination], using IRTE[GATag][7:0] as the vector, while still updating the guest vAPIC backing page IRR as usual. The AMD IOMMU also allows suppressing GAPPI interrupts using the IRTE[GAPPIDis] bit when the GAPPIDisSup feature is available in extended feature register 2. The AMD IOMMU driver sets this bit when the wakeup_intr flag is not set by KVM. Note: amd_iommu_gappi is currently false; a later patch enables it via the kernel command line. [1] https://docs.amd.com/v/u/en-US/48882_3.11_IOMMU_PUB Signed-off-by: Sairaj Kodilkar --- drivers/iommu/amd/amd_iommu_types.h | 4 +++- drivers/iommu/amd/init.c | 3 +++ drivers/iommu/amd/iommu.c | 30 +++++++++++++++++++---------- include/linux/amd-iommu.h | 6 ++++++ 4 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index f9f718087893..26d7a9796e64 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -113,6 +113,7 @@ /* Extended Feature 2 Bits */ #define FEATURE_SEVSNPIO_SUP BIT_ULL(1) #define FEATURE_GCR3TRPMODE BIT_ULL(3) +#define FEATURE_GAPPIDISSUP BIT_ULL(4) #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) #define FEATURE_SNPAVICSUP_GAM(x) \ (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) @@ -1004,7 +1005,8 @@ union irte_ga_lo { no_fault : 1, /* ------ */ ga_log_intr : 1, - rsvd1 : 3, + rsvd1 : 2, + gappi_dis : 1, is_run : 1, /* ------ */ guest_mode : 1, diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 3bdb380d23e9..2e1889f8a9e4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -160,6 +160,9 @@ u8 amd_iommu_hpt_level; /* Guest page table level */ int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; +bool amd_iommu_gappi; +EXPORT_SYMBOL(amd_iommu_gappi); + int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a5f89e93ee41..d89e3ce97e57 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3970,8 +3970,18 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, entry->lo.fields_vapic.is_run = true; entry->lo.fields_vapic.ga_log_intr = false; } else { - entry->lo.fields_vapic.is_run = false; - entry->lo.fields_vapic.ga_log_intr = wakeup_intr; + if (amd_iommu_gappi) { + entry->lo.fields_vapic.gappi_dis = !wakeup_intr && + check_feature2(FEATURE_GAPPIDISSUP); + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.destination = + APICID_TO_IRTE_DEST_LO(apicid); + entry->hi.fields.destination = + APICID_TO_IRTE_DEST_HI(apicid); + } else { + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.ga_log_intr = wakeup_intr; + } } } @@ -3982,15 +3992,15 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, * If the vCPU is scheduled to run on pCPU (@is_running = 1), configure the * Destination with the pCPU's APIC ID, set IsRun, and clear GALogIntr. If the * vCPU is scheduled out (@is_running = 0), clear IsRun and set/clear GALogIntr - * based on input from the caller (e.g. KVM only requests wakeup_intr when the - * vCPU is blocking and requires a notification wake event). This API is - * intended to be used when a vCPU is scheduled in/out (or stops running for - * any reason), to do a fast update of IsRun, GALogIntr, and (conditionally) - * Destination. + * and GAPPIDis based on input from the caller (e.g. KVM only requests + * wakeup_intr when the vCPU is blocking and requires a notification wake + * event). This API is intended to be used when a vCPU is scheduled in/out (or + * stops running for any reason), to do a fast update of IsRun, GALogIntr, + * GAPPIDis and (conditionally) Destination. * - * Per the IOMMU spec, the Destination, IsRun, and GATag fields are not cached - * and thus don't require an invalidation to ensure the IOMMU consumes fresh - * information. + * Per the IOMMU spec, the Destination, IsRun, GATag and GAPPIDis fields are + * not cached and thus don't require an invalidation to ensure the IOMMU + * consumes fresh information. */ int amd_iommu_update_ga(void *data, int apicid, bool wakeup_intr, bool is_running) { diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index a5f1bd6db0ee..de228140ce6e 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -35,6 +35,9 @@ extern int amd_iommu_update_ga(void *data, int apicid, bool wakeup_intr, extern int amd_iommu_activate_guest_mode(void *data, int apicid, bool wakeup_intr); extern int amd_iommu_deactivate_guest_mode(void *data); +/* IOMMU AVIC Flag */ +extern bool amd_iommu_gappi; + #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ static inline int @@ -58,6 +61,9 @@ static inline int amd_iommu_deactivate_guest_mode(void *data) { return 0; } + +#define amd_iommu_gappi false + #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ int amd_iommu_get_num_iommus(void); -- 2.34.1